Mr_Fang/Power-Pico
1
0
Fork 0
mirror of https://github.com/No-Chicken/Power-Pico.git synced 2026-04-03 13:02:36 +08:00
Code Issues Packages Projects Releases Wiki Activity

fixed mem ALIGN bug

Browse Source
This commit is contained in:
不吃油炸鸡
2026-02-28 11:29:32 +08:00
committed by kingham
parent 4beb585fe6
commit fb866b90fd
4 changed files with 223 additions and 264 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
software/Power_Pico/MDK-ARM/DebugConfig/power_pico_STM32F411CEUx.dbgconf
View File

@@ -1,41 +0,0 @@
// File: STM32F401xBCDE_411xCE.dbgconf
// Version: 1.0.0
// Note: refer to STM32F401xB/C STM32F401xD/E reference manual (RM0368)
// refer to STM32F401xB/C STM32F401xD/E datasheet
// refer to STM32F411xC/E reference manual (RM0383)
// refer to STM32F411xC/E datasheet
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

4
software/Power_Pico/Middlewares/LVGL/lv_conf.h
View File

@@ -443,11 +443,11 @@
#define LV_ATTRIBUTE_FLUSH_READY #define LV_ATTRIBUTE_FLUSH_READY
/*Required alignment size for buffers*/ /*Required alignment size for buffers*/
#define LV_ATTRIBUTE_MEM_ALIGN_SIZE 1 #define LV_ATTRIBUTE_MEM_ALIGN_SIZE 32
/*Will be added where memories needs to be aligned (with -Os data might not be aligned to boundary by default). /*Will be added where memories needs to be aligned (with -Os data might not be aligned to boundary by default).
* E.g. __attribute__((aligned(4)))*/ * E.g. __attribute__((aligned(4)))*/
#define LV_ATTRIBUTE_MEM_ALIGN #define LV_ATTRIBUTE_MEM_ALIGN __attribute__((aligned(LV_ATTRIBUTE_MEM_ALIGN_SIZE)))
/*Attribute to mark large constant arrays for example font's bitmaps*/ /*Attribute to mark large constant arrays for example font's bitmaps*/
#define LV_ATTRIBUTE_LARGE_CONST #define LV_ATTRIBUTE_LARGE_CONST

2
software/Power_Pico/STM32F411XX_FLASH.ld
View File

@@ -62,7 +62,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
MEMORY MEMORY
{ {
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K FLASH (rx) : ORIGIN = 0x8010000, LENGTH = 512K
} }
/* Define output sections */ /* Define output sections */