mirror of
https://github.com/No-Chicken/Power-Pico.git
synced 2026-04-03 13:02:36 +08:00
597 lines
19 KiB
C
597 lines
19 KiB
C
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/**
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* FUSB302_UFP.c
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*
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* Updated on: Jan 4, 2021
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* Author: Ryan Ma
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*
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* Minimalist USB PD implement with only UFP(device) functionality
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* Requires only stdint.h and string.h
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* No use of bit-field for better cross-platform compatibility
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*
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* FUSB302 can support PD3.0 with limitations and workarounds
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* - Do not have enough FIFO for unchunked message, use chunked message instead
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* - VBUS sense low threshold at 4V, disable vbus_sense if request PPS below 4V
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*
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*/
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#include <string.h>
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#include "FUSB302_UFP.h"
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/* Switches0 : 02h */
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#define PU_EN2 (0x01 << 7)
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#define PU_EN1 (0x01 << 6)
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#define VCONN_CC2 (0x01 << 5)
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#define VCONN_CC1 (0x01 << 4)
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#define MEAS_CC2 (0x01 << 3)
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#define MEAS_CC1 (0x01 << 2)
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#define PDWN2 (0x01 << 1)
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#define PDWN1 (0x01 << 0)
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/* Switches1 : 03h */
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#define POWERROLE (0x01 << 7)
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#define SPECREV1 (0x01 << 6)
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#define SPECREV0 (0x01 << 5)
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#define DATAROLE (0x01 << 4)
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#define AUTO_CRC (0x01 << 2)
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#define TXCC2 (0x01 << 1)
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#define TXCC1 (0x01 << 0)
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/* Measure : 04h */
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#define MEAS_VBUS (0x01 << 6)
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/* Control0 : 06h */
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#define TX_FLUSH (0x01 << 6)
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#define INT_MASK (0x01 << 5)
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#define HOST_CUR_MASK (0x03 << 2)
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#define HOST_CUR_3A0 (0x03 << 2)
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#define HOST_CUR_1A5 (0x02 << 2)
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#define HOST_CUR_USB (0x01 << 2)
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#define AUTO_PRE (0x01 << 1)
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#define TX_START (0x01 << 0)
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/* Control1 : 07h */
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#define ENSOP2DB (0x01 << 6)
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#define ENSOP1DB (0x01 << 5)
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#define BIST_MODE2 (0x01 << 4)
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#define RX_FLUSH (0x01 << 2)
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#define ENSOP2 (0x01 << 1)
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#define ENSOP1 (0x01 << 0)
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/* Control2 : 08h */
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#define WAKE_EN (0x01 << 3)
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#define MODE_MASK (0x03 << 1)
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#define MODE_DFP (0x03 << 1)
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#define MODE_UFP (0x02 << 1)
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#define MODE_DRP (0x01 << 1)
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#define TOGGLE (0x01 << 0)
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/* Control3 : 09h */
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#define SEND_HARDRESET (0x01 << 6)
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#define BIST_TMODE (0x01 << 5) /* on FUSB302B only */
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#define AUTO_HARDRESET (0x01 << 4)
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#define AUTO_SOFTRESET (0x01 << 3)
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#define N_RETRIES_MASK (0x03 << 1)
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#define N_RETRIES(n) ((n) << 1)
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#define AUTO_RETRY (0x01 << 0)
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/* Mask : 0Ah */
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#define M_VBUSOK (0x01 << 7)
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#define M_ACTIVITY (0x01 << 6)
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#define M_COMP_CHNG (0x01 << 5)
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#define M_CRC_CHK (0x01 << 4)
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#define M_ALERT (0x01 << 3)
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#define M_WAKE (0x01 << 2)
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#define M_COLLISION (0x01 << 1)
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#define M_BC_LVL (0x01 << 0)
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/* Power : 0Bh */
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#define PWR_INT_OSC (0x01 << 3) /* Enable internal oscillator */
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#define PWR_MEASURE (0x01 << 2) /* Measure block powered */
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#define PWR_RECEIVER (0x01 << 1) /* Receiver powered and current reference for Measure block */
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#define PWR_BANDGAP (0x01 << 0) /* Bandgap and wake circuitry */
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/* Reset : 0Ch */
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#define PD_RESET (0x01 << 1)
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#define SW_RES (0x01 << 0)
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/* Maska : 0Eh */
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#define M_OCP_TEMP (0x01 << 7)
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#define M_TOGDONE (0x01 << 6)
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#define M_SOFTFAIL (0x01 << 5)
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#define M_RETRYFAIL (0x01 << 4)
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#define M_HARDSENT (0x01 << 3)
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#define M_TXSENT (0x01 << 2)
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#define M_SOFTRST (0x01 << 1)
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#define M_HARDRST (0x01 << 0)
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/* Maskb : 0Fh */
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#define M_GCRCSENT (0x01 << 0)
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/* Status0a : 3Ch */
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#define SOFTFAIL (0x01 << 5)
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#define RETRYFAIL (0x01 << 4)
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#define POWER3_2 (0x01 << 2)
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#define SOFTRST (0x01 << 1)
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#define HARDRST (0x01 << 0)
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/* Status1a : 3Dh */
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#define TOGSS_MASK (0x07 << 3)
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#define TOGSS_RUNNING (0x00 << 3)
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#define TOGSS_SRC1 (0x01 << 3)
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#define TOGSS_SRC2 (0x02 << 3)
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#define TOGSS_SNK1 (0x05 << 3)
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#define TOGSS_SNK2 (0x06 << 3)
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#define TOGSS_AUDIOA (0x07 << 3)
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#define RXSOP2DB (0x01 << 2)
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#define RXSOP1DB (0x01 << 1)
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#define RXSOP (0x01 << 0)
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/* Interrupta : 3Eh */
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#define I_OCP_TEMP (0x01 << 7)
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#define I_TOGDONE (0x01 << 6)
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#define I_SOFTFAIL (0x01 << 5)
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#define I_RETRYFAIL (0x01 << 4)
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#define I_HARDSENT (0x01 << 3)
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#define I_TXSENT (0x01 << 2)
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#define I_SOFTRST (0x01 << 1)
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#define I_HARDRST (0x01 << 0)
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/* Interruptb : 3Fh */
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#define I_GCRCSENT (0x01 << 0)
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/* Status0 : 40h */
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#define VBUSOK (0x01 << 7)
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#define ACTIVITY (0x01 << 6)
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#define COMP (0x01 << 5)
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#define CRC_CHK (0x01 << 4)
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#define ALERT (0x01 << 3)
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#define WAKE (0x01 << 2)
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#define BC_LVL_MASK (0x03 << 0)
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#define BC_LVL_LT200 (0x00 << 0)
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#define BC_LVL_200_660 (0x01 << 0)
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#define BC_LVL_660_1230 (0x02 << 0)
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#define BC_LVL_GT1230 (0x03 << 0)
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/* Status1 : 41h */
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#define RXSOP2 (0x01 << 7)
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#define RXSOP1 (0x01 << 6)
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#define RX_EMPTY (0x01 << 5)
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#define RX_FULL (0x01 << 4)
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#define TX_EMPTY (0x01 << 3)
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#define TX_FULL (0x01 << 2)
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#define OVRTEMP (0x01 << 1)
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#define OCP (0x01 << 0)
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/* Interrupt : 42h */
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#define I_VBUSOK (0x01 << 7)
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#define I_ACTIVITY (0x01 << 6)
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#define I_COMP_CHNG (0x01 << 5)
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#define I_CRC_CHK (0x01 << 4)
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#define I_ALERT (0x01 << 3)
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#define I_WAKE (0x01 << 2)
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#define I_COLLISION (0x01 << 1)
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#define I_BC_LVL (0x01 << 0)
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#define ADDRESS_DEVICE_ID 0x01
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#define ADDRESS_SWITCHES0 0x02
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#define ADDRESS_SWITCHES1 0x03
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#define ADDRESS_MEASURE 0x04
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#define ADDRESS_SLICE 0x05
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#define ADDRESS_CONTROL0 0x06
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#define ADDRESS_CONTROL1 0x07
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#define ADDRESS_CONTROL2 0x08
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#define ADDRESS_CONTROL3 0x09
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#define ADDRESS_MASK 0x0A
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#define ADDRESS_POWER 0x0B
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#define ADDRESS_RESET 0x0C
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#define ADDRESS_MASKA 0x0E
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#define ADDRESS_MASKB 0x0F
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#define ADDRESS_STATUS0A 0x3C
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#define ADDRESS_STATUS1A 0x3D
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#define ADDRESS_INTERRUPTA 0x3E
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#define ADDRESS_INTERRUPTB 0x3F
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#define ADDRESS_STATUS0 0x40
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#define ADDRESS_STATUS1 0x41
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#define ADDRESS_INTERRUPT 0x42
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#define ADDRESS_FIFOS 0x43
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#define REG_DEVICE_ID dev->reg_control[ADDRESS_DEVICE_ID - ADDRESS_DEVICE_ID]
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#define REG_SWITCHES0 dev->reg_control[ADDRESS_SWITCHES0 - ADDRESS_DEVICE_ID]
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#define REG_SWITCHES1 dev->reg_control[ADDRESS_SWITCHES1 - ADDRESS_DEVICE_ID]
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#define REG_MEASURE dev->reg_control[ADDRESS_MEASURE - ADDRESS_DEVICE_ID]
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#define REG_SLICE dev->reg_control[ADDRESS_SLICE - ADDRESS_DEVICE_ID]
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#define REG_CONTROL0 dev->reg_control[ADDRESS_CONTROL0 - ADDRESS_DEVICE_ID]
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#define REG_CONTROL1 dev->reg_control[ADDRESS_CONTROL1 - ADDRESS_DEVICE_ID]
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#define REG_CONTROL2 dev->reg_control[ADDRESS_CONTROL2 - ADDRESS_DEVICE_ID]
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#define REG_CONTROL3 dev->reg_control[ADDRESS_CONTROL3 - ADDRESS_DEVICE_ID]
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#define REG_MASK dev->reg_control[ADDRESS_MASK - ADDRESS_DEVICE_ID]
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#define REG_POWER dev->reg_control[ADDRESS_POWER - ADDRESS_DEVICE_ID]
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#define REG_RESET dev->reg_control[ADDRESS_RESET - ADDRESS_DEVICE_ID]
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#define REG_MASKA dev->reg_control[ADDRESS_MASKA - ADDRESS_DEVICE_ID]
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#define REG_MASKB dev->reg_control[ADDRESS_MASKB - ADDRESS_DEVICE_ID]
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#define REG_STATUS0A dev->reg_status[ADDRESS_STATUS0A - ADDRESS_STATUS0A]
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#define REG_STATUS1A dev->reg_status[ADDRESS_STATUS1A - ADDRESS_STATUS0A]
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#define REG_INTERRUPTA dev->reg_status[ADDRESS_INTERRUPTA - ADDRESS_STATUS0A]
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#define REG_INTERRUPTB dev->reg_status[ADDRESS_INTERRUPTB - ADDRESS_STATUS0A]
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#define REG_STATUS0 dev->reg_status[ADDRESS_STATUS0 - ADDRESS_STATUS0A]
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#define REG_STATUS1 dev->reg_status[ADDRESS_STATUS1 - ADDRESS_STATUS0A]
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#define REG_INTERRUPT dev->reg_status[ADDRESS_INTERRUPT - ADDRESS_STATUS0A]
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enum FUSB302_transmit_data_tokens_t {
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TX_TOKEN_TXON = 0xA1,
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TX_TOKEN_SOP1 = 0x12,
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TX_TOKEN_SOP2 = 0x13,
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TX_TOKEN_SOP3 = 0x1B,
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TX_TOKEN_RESET1 = 0x15,
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TX_TOKEN_RESET2 = 0x16,
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TX_TOKEN_PACKSYM = 0x80,
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TX_TOKEN_JAM_CRC = 0xFF,
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TX_TOKEN_EOP = 0x14,
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TX_TOKEN_TXOFF = 0xFE,
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};
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enum FUSB302_state_t {
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FUSB302_STATE_UNATTACHED = 0,
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FUSB302_STATE_ATTACHED
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};
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#define FUSB302_ERR_MSG(s) s
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#define REG_READ(addr, data, count) do { \
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if (reg_read(dev, addr, data, count) != FUSB302_SUCCESS) { return FUSB302_ERR_READ_DEVICE; } \
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} while(0)
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#define REG_WRITE(addr, data, count) do { \
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if (reg_write(dev, addr, data, count) != FUSB302_SUCCESS) { return FUSB302_ERR_WRITE_DEVICE; } \
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} while(0)
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static inline FUSB302_ret_t reg_read(FUSB302_dev_t *dev, uint8_t address, uint8_t *data, uint8_t count)
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{
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FUSB302_ret_t ret = dev->i2c_read(dev->i2c_address, address, data, count);
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if (ret != FUSB302_SUCCESS) {
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dev->err_msg = FUSB302_ERR_MSG("Fail to read register");
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}
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return ret;
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}
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static inline FUSB302_ret_t reg_write(FUSB302_dev_t *dev, uint8_t address, uint8_t *data, uint8_t count)
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{
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FUSB302_ret_t ret = dev->i2c_write(dev->i2c_address, address, data, count);
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if (ret != FUSB302_SUCCESS) {
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dev->err_msg = FUSB302_ERR_MSG("Fail to write register");
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}
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return ret;
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}
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static FUSB302_ret_t FUSB302_read_cc_lvl(FUSB302_dev_t *dev, uint8_t * cc_value)
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{
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/* 00: < 200 mV : vRa
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01: >200 mV, <660 mV : vRd-USB
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10: >660 mV, <1.23 V : vRd-1.5
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11: >1.23 V : vRd-3.0 */
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uint8_t cc, cc_verify;
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REG_READ(ADDRESS_STATUS0, ®_STATUS0, 1);
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cc = REG_STATUS0 & BC_LVL_MASK;
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for (uint8_t i = 0; i < 5; i++) {
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REG_READ(ADDRESS_STATUS0, ®_STATUS0, 1);
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cc_verify = REG_STATUS0 & BC_LVL_MASK;
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if (cc != cc_verify) {
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return FUSB302_BUSY;
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}
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}
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*cc_value = cc;
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return FUSB302_SUCCESS;
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}
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static FUSB302_ret_t FUSB302_read_incoming_packet(FUSB302_dev_t *dev, FUSB302_event_t * events)
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{
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uint8_t len, b[3];
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REG_READ(ADDRESS_FIFOS, b, 3);
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dev->rx_header = ((uint16_t)b[2] << 8) | b[1];
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len = (dev->rx_header >> 12) & 0x7;
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REG_READ(ADDRESS_FIFOS, dev->rx_buffer, len * 4 + 4); /* add 4 to len to read CRC out */
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if (events) {
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*events |= FUSB302_EVENT_RX_SOP;
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}
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return FUSB302_SUCCESS;
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}
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static FUSB302_ret_t FUSB302_state_unattached(FUSB302_dev_t *dev, FUSB302_event_t * events)
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{
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REG_READ(ADDRESS_STATUS0, ®_STATUS0, 1);
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if (REG_STATUS0 & VBUSOK) {
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/* enable internal oscillator */
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REG_POWER = PWR_BANDGAP | PWR_RECEIVER | PWR_MEASURE | PWR_INT_OSC;
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REG_WRITE(ADDRESS_POWER, ®_POWER, 1);
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dev->delay_ms(2);
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/* read cc1 */
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REG_SWITCHES0 = PDWN1 | PDWN2 | MEAS_CC1;
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REG_SWITCHES1 = SPECREV0;
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REG_MEASURE = 49;
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REG_WRITE(ADDRESS_SWITCHES0, ®_SWITCHES0, 3);
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dev->delay_ms(2);
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while (FUSB302_read_cc_lvl(dev, &dev->cc1) != FUSB302_SUCCESS) {
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dev->delay_ms(2);
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}
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/* read cc2 */
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REG_SWITCHES0 = PDWN1 | PDWN2 | MEAS_CC2;
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REG_WRITE(ADDRESS_SWITCHES0, ®_SWITCHES0, 1);
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dev->delay_ms(2);
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while (FUSB302_read_cc_lvl(dev, &dev->cc2) != FUSB302_SUCCESS) {
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dev->delay_ms(2);
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}
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/* clear interrupt */
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REG_READ(ADDRESS_INTERRUPTA, ®_INTERRUPTA, 2);
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dev->interrupta = 0;
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dev->interruptb = 0;
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/* enable tx on cc pin */
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if (dev->cc1 > 0) {
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REG_SWITCHES0 = PDWN1 | PDWN2 | MEAS_CC1;
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REG_SWITCHES1 = SPECREV0 | AUTO_CRC | TXCC1;
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//REG_SWITCHES1 = SPECREV0 | TXCC1;
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} else if (dev->cc2 > 0) {
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REG_SWITCHES0 = PDWN1 | PDWN2 | MEAS_CC2;
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REG_SWITCHES1 = SPECREV0 | AUTO_CRC | TXCC2;
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//REG_SWITCHES1 = SPECREV0 | TXCC2;
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} else {
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REG_SWITCHES0 = PDWN1 | PDWN2;
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REG_SWITCHES1 = SPECREV0;
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}
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REG_WRITE(ADDRESS_SWITCHES0, ®_SWITCHES0, 2);
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/* update state */
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dev->state = FUSB302_STATE_ATTACHED;
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if (events) {
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*events |= FUSB302_EVENT_ATTACHED;
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}
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}
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return FUSB302_SUCCESS;
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}
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static FUSB302_ret_t FUSB302_state_attached(FUSB302_dev_t *dev, FUSB302_event_t * events)
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{
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REG_READ(ADDRESS_STATUS0A, ®_STATUS0A, 7);
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dev->interrupta |= REG_INTERRUPTA;
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dev->interruptb |= REG_INTERRUPTB;
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if (dev->vbus_sense && ((REG_STATUS0 & VBUSOK) == 0)) {
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/* reset cc pins to pull down */
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REG_SWITCHES0 = PDWN1 | PDWN2;
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REG_SWITCHES1 = SPECREV0;
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REG_MEASURE = 49;
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REG_WRITE(ADDRESS_SWITCHES0, ®_SWITCHES0, 3);
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/* turn off internal oscillator */
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REG_POWER = PWR_BANDGAP | PWR_RECEIVER | PWR_MEASURE;
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REG_WRITE(ADDRESS_POWER, ®_POWER, 1);
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/* update state */
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dev->state = FUSB302_STATE_UNATTACHED;
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if (events) {
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*events |= FUSB302_EVENT_DETACHED;
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}
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return FUSB302_SUCCESS;
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}
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if (REG_STATUS0A & HARDRST) {
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uint8_t reg_control = PD_RESET;
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REG_WRITE(ADDRESS_RESET, ®_control, 1);
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return FUSB302_SUCCESS;
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}
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if (dev->interruptb & I_GCRCSENT) {
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dev->interruptb &= ~I_GCRCSENT;
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if (events) {
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*events |= FUSB302_EVENT_GOOD_CRC_SENT;
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}
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}
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if ((REG_STATUS1 & RX_EMPTY) == 0) {
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if (FUSB302_read_incoming_packet(dev, events) != FUSB302_SUCCESS) {
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uint8_t rx_flush = REG_CONTROL1 | RX_FLUSH;
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reg_write(dev, ADDRESS_CONTROL1, &rx_flush, 1);
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}
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}
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return FUSB302_SUCCESS;
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}
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FUSB302_ret_t FUSB302_init(FUSB302_dev_t *dev)
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{
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if (dev->i2c_address == 0) {
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dev->err_msg = FUSB302_ERR_MSG("Invalid i2c address");
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return FUSB302_ERR_PARAM;
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}
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if (dev->i2c_read == 0) {
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dev->err_msg = FUSB302_ERR_MSG("Invalid i2c_read function");
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return FUSB302_ERR_PARAM;
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}
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if (dev->i2c_write == 0) {
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dev->err_msg = FUSB302_ERR_MSG("Invalid i2c_write function");
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return FUSB302_ERR_PARAM;
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}
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if (reg_read(dev, ADDRESS_DEVICE_ID, &dev->reg_control[1], 1) != FUSB302_SUCCESS) {
|
|
dev->err_msg = FUSB302_ERR_MSG("Device not found");
|
|
return FUSB302_ERR_READ_DEVICE;
|
|
}
|
|
|
|
if ((dev->reg_control[1] & 0x80) == 0) {
|
|
dev->err_msg = FUSB302_ERR_MSG("Invalid device version");
|
|
return FUSB302_ERR_DEVICE_ID;
|
|
}
|
|
|
|
dev->state = FUSB302_STATE_UNATTACHED;
|
|
dev->rx_header = 0;
|
|
memset(dev->rx_buffer, 0, sizeof(dev->rx_buffer));
|
|
|
|
/* restore default settings */
|
|
REG_RESET = SW_RES;
|
|
REG_WRITE(ADDRESS_RESET, ®_RESET, 1);
|
|
|
|
/* fetch all R/W registers */
|
|
REG_READ(ADDRESS_DEVICE_ID, ®_DEVICE_ID, 15);
|
|
|
|
/* configure switchs and comparators */
|
|
REG_SWITCHES0 = PDWN1 | PDWN2;
|
|
REG_SWITCHES1 = SPECREV0;
|
|
REG_MEASURE = 49;
|
|
REG_WRITE(ADDRESS_SWITCHES0, ®_SWITCHES0, 3);
|
|
|
|
/* configure auto retries */
|
|
REG_CONTROL3 &= ~N_RETRIES_MASK;
|
|
REG_CONTROL3 |= N_RETRIES(3) | AUTO_RETRY;
|
|
REG_WRITE(ADDRESS_CONTROL3, ®_CONTROL3, 1);
|
|
|
|
/* configure interrupt mask */
|
|
REG_MASK = 0xFF;
|
|
REG_MASK &= ~(M_VBUSOK | M_ACTIVITY | M_COLLISION | M_ALERT | M_CRC_CHK);
|
|
REG_WRITE(ADDRESS_MASK, ®_MASK, 1);
|
|
|
|
/* configure interrupt maska/maskb */
|
|
REG_MASKA = 0xFF;
|
|
REG_MASKA &= ~(M_RETRYFAIL | M_HARDSENT | M_TXSENT | M_HARDRST);
|
|
REG_WRITE(ADDRESS_MASKA, ®_MASKA, 1);
|
|
REG_MASKB = 0xFF;
|
|
REG_MASKB &= ~(M_GCRCSENT);
|
|
REG_WRITE(ADDRESS_MASKB, ®_MASKB, 1);
|
|
|
|
/* enable interrupt */
|
|
REG_CONTROL0 &= ~INT_MASK;
|
|
REG_WRITE(ADDRESS_CONTROL0, ®_CONTROL0, 1);
|
|
|
|
/* Power on, enable VUSB detection */
|
|
REG_POWER = PWR_BANDGAP | PWR_RECEIVER | PWR_MEASURE;
|
|
REG_WRITE(ADDRESS_POWER, ®_POWER, 1);
|
|
|
|
dev->vbus_sense = 1;
|
|
dev->err_msg = FUSB302_ERR_MSG("");
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_pd_reset(FUSB302_dev_t *dev)
|
|
{
|
|
uint8_t reg = PD_RESET;
|
|
REG_WRITE(ADDRESS_RESET, ®, 1);
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_pdwn_cc(FUSB302_dev_t *dev, uint8_t enable)
|
|
{
|
|
REG_SWITCHES0 = enable ? (PDWN1 | PDWN2) : 0;
|
|
REG_WRITE(ADDRESS_SWITCHES0, ®_SWITCHES0, 1);
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_set_vbus_sense(FUSB302_dev_t *dev, uint8_t enable)
|
|
{
|
|
if (dev->vbus_sense != enable) {
|
|
if (enable) {
|
|
REG_MASK &= ~M_VBUSOK; /* enable VBUSOK interrupt */
|
|
} else {
|
|
REG_MASK |= M_VBUSOK; /* disable VBUSOK interrupt */
|
|
}
|
|
REG_WRITE(ADDRESS_MASK, ®_MASK, 1);
|
|
dev->vbus_sense = enable;
|
|
}
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_get_ID(FUSB302_dev_t *dev, uint8_t * version_ID, uint8_t * revision_ID)
|
|
{
|
|
if (dev && (REG_DEVICE_ID & 0x80)) {
|
|
if (version_ID) {
|
|
*version_ID = (REG_DEVICE_ID >> 4) & 0x7;
|
|
}
|
|
if (revision_ID) {
|
|
*revision_ID = (REG_DEVICE_ID >> 0) & 0xF;
|
|
}
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
return FUSB302_ERR_PARAM;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_get_cc(FUSB302_dev_t *dev, uint8_t *cc1, uint8_t *cc2)
|
|
{
|
|
if (cc1) {
|
|
*cc1 = dev->cc1;
|
|
}
|
|
if (cc2) {
|
|
*cc2 = dev->cc2;
|
|
}
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_get_vbus_level(FUSB302_dev_t *dev, uint8_t *vbus)
|
|
{
|
|
uint8_t reg_control;
|
|
REG_READ(ADDRESS_STATUS0, ®_control, 1);
|
|
*vbus = reg_control & VBUSOK ? 1 : 0;
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_get_message(FUSB302_dev_t *dev, uint16_t * header, uint32_t * data)
|
|
{
|
|
if (header) {
|
|
*header = dev->rx_header;
|
|
}
|
|
if (data) {
|
|
uint8_t len = (dev->rx_header >> 12) & 0x7;
|
|
memcpy(data, dev->rx_buffer, len * 4);
|
|
}
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_tx_sop(FUSB302_dev_t *dev, uint16_t header, const uint32_t *data)
|
|
{
|
|
uint8_t buf[40];
|
|
uint8_t * pbuf = buf;
|
|
uint8_t obj_count = ((header >> 12) & 7);
|
|
*pbuf++ = (uint8_t)TX_TOKEN_SOP1;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_SOP1;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_SOP1;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_SOP2;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_PACKSYM | ((obj_count << 2) + 2);
|
|
*pbuf++ = header & 0xFF; header >>= 8;
|
|
*pbuf++ = header & 0xFF;
|
|
for (uint8_t i = 0; i < obj_count; i++) {
|
|
uint32_t d = *data++;
|
|
*pbuf++ = d & 0xFF; d >>= 8;
|
|
*pbuf++ = d & 0xFF; d >>= 8;
|
|
*pbuf++ = d & 0xFF; d >>= 8;
|
|
*pbuf++ = d & 0xFF;
|
|
}
|
|
*pbuf++ = (uint8_t)TX_TOKEN_JAM_CRC;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_EOP;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_TXOFF;
|
|
*pbuf++ = (uint8_t)TX_TOKEN_TXON;
|
|
REG_WRITE(ADDRESS_FIFOS, buf, pbuf - buf);
|
|
dev->delay_ms(2);
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_tx_hard_reset(FUSB302_dev_t *dev)
|
|
{
|
|
uint8_t reg_control = REG_CONTROL3;
|
|
reg_control |= SEND_HARDRESET;
|
|
REG_WRITE(ADDRESS_CONTROL3, ®_control, 1);
|
|
dev->delay_ms(6);
|
|
reg_control = PD_RESET;
|
|
REG_WRITE(ADDRESS_RESET, ®_control, 1);
|
|
return FUSB302_SUCCESS;
|
|
}
|
|
|
|
FUSB302_ret_t FUSB302_alert(FUSB302_dev_t *dev, FUSB302_event_t * events)
|
|
{
|
|
FUSB302_ret_t (* const handler[]) (FUSB302_dev_t *, FUSB302_event_t *) = {
|
|
FUSB302_state_unattached,
|
|
FUSB302_state_attached
|
|
};
|
|
if (dev->state < sizeof(handler) / sizeof(handler[0])) {
|
|
return handler[dev->state](dev, events);
|
|
}
|
|
dev->state = FUSB302_STATE_UNATTACHED;
|
|
return FUSB302_SUCCESS;
|
|
}
|