mirror of
https://github.com/No-Chicken/Power-Pico.git
synced 2026-04-03 13:02:36 +08:00
加入GPIO下拉
This commit is contained in:
不吃油炸鸡
File diff suppressed because one or more lines are too long
@@ -66,7 +66,7 @@ void MX_GPIO_Init(void)
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/*Configure GPIO pin : PB10 */
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/*Configure GPIO pin : PB10 */
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GPIO_InitStruct.Pin = GPIO_PIN_10;
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GPIO_InitStruct.Pin = GPIO_PIN_10;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Pull = GPIO_PULLDOWN;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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@@ -253,7 +253,7 @@
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<Group>
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<Group>
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<GroupName>Application/User/Core</GroupName>
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<GroupName>Application/User/Core</GroupName>
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<tvExp>0</tvExp>
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<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<tvExpOptDlg>0</tvExpOptDlg>
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<cbSel>0</cbSel>
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<cbSel>0</cbSel>
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<RteFlg>0</RteFlg>
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<RteFlg>0</RteFlg>
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@@ -1,775 +0,0 @@
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/*
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* FreeRTOS Kernel V10.3.1
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM4F port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef __VFP_FP__
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#error This port can only be used when the project options are configured to enable hardware floating point support.
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#endif
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#ifndef configSYSTICK_CLOCK_HZ
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#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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/* Ensure the SysTick is clocked at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#else
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/* The way the SysTick is clocked is not modified in case it is not the same
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as the core. */
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#define portNVIC_SYSTICK_CLK_BIT ( 0 )
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#endif
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/* Constants required to manipulate the core. Registers first... */
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#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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/* ...then bits in the registers. */
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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r0p1 port. */
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#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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#define portPRIGROUP_SHIFT ( 8UL )
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/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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#define portVECTACTIVE_MASK ( 0xFFUL )
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/* Constants required to manipulate the VFP. */
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#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000 )
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#define portINITIAL_EXC_RETURN ( 0xfffffffd )
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/* The systick is a 24-bit counter. */
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#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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/* For strict compliance with the Cortex-M spec the task start address should
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* A fiddle factor to estimate the number of SysTick counts that would have
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occurred while the SysTick counter is stopped during tickless idle
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calculations. */
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#define portMISSED_COUNTS_FACTOR ( 45UL )
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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void vPortSetupTimerInterrupt( void );
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/*
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* Exception handlers.
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*/
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void xPortPendSVHandler( void ) __attribute__ (( naked ));
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void xPortSysTickHandler( void );
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void vPortSVCHandler( void ) __attribute__ (( naked ));
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/*
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* Start first task is a separate function so it can be tested in isolation.
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*/
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static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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/*
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* Function to enable the VFP.
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*/
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static void vPortEnableVFP( void ) __attribute__ (( naked ));
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/*
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* Used to catch tasks that attempt to return from their implementing function.
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*/
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static void prvTaskExitError( void );
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/*-----------------------------------------------------------*/
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* The number of SysTick increments that make up one tick period.
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*/
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#if( configUSE_TICKLESS_IDLE == 1 )
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static uint32_t ulTimerCountsForOneTick = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*
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* The maximum number of tick periods that can be suppressed is limited by the
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* 24 bit resolution of the SysTick timer.
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*/
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#if( configUSE_TICKLESS_IDLE == 1 )
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static uint32_t xMaximumPossibleSuppressedTicks = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*
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* Compensate for the CPU cycles that pass while the SysTick is stopped (low
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* power functionality only.
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*/
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#if( configUSE_TICKLESS_IDLE == 1 )
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static uint32_t ulStoppedTimerCompensation = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*
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* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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* FreeRTOS API functions are not called from interrupts that have been assigned
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* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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*/
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#if( configASSERT_DEFINED == 1 )
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static uint8_t ucMaxSysCallPriority = 0;
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static uint32_t ulMaxPRIGROUPValue = 0;
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static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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#endif /* configASSERT_DEFINED */
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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/* Simulate the stack frame as it would be created by a context switch
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interrupt. */
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/* Offset added to account for the way the MCU uses the stack on entry/exit
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of interrupts, and to ensure alignment. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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/* Save code space by skipping register initialisation. */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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/* A save method is being used that requires each task to maintain its
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own exec return value. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_EXC_RETURN;
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pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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static void prvTaskExitError( void )
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{
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volatile uint32_t ulDummy = 0;
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/* A function that implements a task must not exit or attempt to return to
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its caller as there is nothing to return to. If a task wants to exit it
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should instead call vTaskDelete( NULL ).
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Artificially force an assert() to be triggered if configASSERT() is
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defined, then stop here so application writers can catch the error. */
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configASSERT( uxCriticalNesting == ~0UL );
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portDISABLE_INTERRUPTS();
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while( ulDummy == 0 )
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{
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/* This file calls prvTaskExitError() after the scheduler has been
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started to remove a compiler warning about the function being defined
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but never called. ulDummy is used purely to quieten other warnings
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about code appearing after this function is called - making ulDummy
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volatile makes the compiler think the function could return and
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therefore not output an 'unreachable code' warning for code that appears
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after it. */
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}
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}
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/*-----------------------------------------------------------*/
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void vPortSVCHandler( void )
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{
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__asm volatile (
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" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n" /* Restore the task stack pointer. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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" bx r14 \n"
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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);
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}
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/*-----------------------------------------------------------*/
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static void prvPortStartFirstTask( void )
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{
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the SVC stack
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for lazy saving of FPU registers. */
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__asm volatile(
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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" msr control, r0 \n"
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" cpsie i \n" /* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc 0 \n" /* System call to start first task. */
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" nop \n"
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);
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}
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/*-----------------------------------------------------------*/
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||||||
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||||||
/*
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* See header file for description.
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*/
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BaseType_t xPortStartScheduler( void )
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||||||
{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* This port can be used on all revisions of the Cortex-M7 core other than
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the r0p1 parts. r0p1 parts should use the port from the
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/source/portable/GCC/ARM_CM7/r0p1 directory. */
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configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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#if( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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||||||
functions can be called. ISR safe functions are those that end in
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||||||
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
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||||||
ensure interrupt entry is as fast and simple as possible.
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||||||
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Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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||||||
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||||||
/* Determine the number of priority bits available. First write to all
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possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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||||||
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||||||
/* Read the value back to see how many bits stuck. */
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||||||
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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||||||
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||||||
/* Use the same mask on the maximum system call priority. */
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||||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
|
||||||
|
|
||||||
/* Calculate the maximum acceptable priority group value for the number
|
|
||||||
of bits read back. */
|
|
||||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
|
||||||
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
||||||
{
|
|
||||||
ulMaxPRIGROUPValue--;
|
|
||||||
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef __NVIC_PRIO_BITS
|
|
||||||
{
|
|
||||||
/* Check the CMSIS configuration that defines the number of
|
|
||||||
priority bits matches the number of priority bits actually queried
|
|
||||||
from the hardware. */
|
|
||||||
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef configPRIO_BITS
|
|
||||||
{
|
|
||||||
/* Check the FreeRTOS configuration that defines the number of
|
|
||||||
priority bits matches the number of priority bits actually queried
|
|
||||||
from the hardware. */
|
|
||||||
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Shift the priority group value back to its position within the AIRCR
|
|
||||||
register. */
|
|
||||||
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
|
|
||||||
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
|
|
||||||
|
|
||||||
/* Restore the clobbered interrupt priority register to its original
|
|
||||||
value. */
|
|
||||||
*pucFirstUserPriorityRegister = ulOriginalPriority;
|
|
||||||
}
|
|
||||||
#endif /* conifgASSERT_DEFINED */
|
|
||||||
|
|
||||||
/* Make PendSV and SysTick the lowest priority interrupts. */
|
|
||||||
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
|
||||||
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
|
||||||
|
|
||||||
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
|
||||||
here already. */
|
|
||||||
vPortSetupTimerInterrupt();
|
|
||||||
|
|
||||||
/* Initialise the critical nesting count ready for the first task. */
|
|
||||||
uxCriticalNesting = 0;
|
|
||||||
|
|
||||||
/* Ensure the VFP is enabled - it should be anyway. */
|
|
||||||
vPortEnableVFP();
|
|
||||||
|
|
||||||
/* Lazy save always. */
|
|
||||||
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
|
||||||
|
|
||||||
/* Start the first task. */
|
|
||||||
prvPortStartFirstTask();
|
|
||||||
|
|
||||||
/* Should never get here as the tasks will now be executing! Call the task
|
|
||||||
exit error function to prevent compiler warnings about a static function
|
|
||||||
not being called in the case that the application writer overrides this
|
|
||||||
functionality by defining configTASK_RETURN_ADDRESS. Call
|
|
||||||
vTaskSwitchContext() so link time optimisation does not remove the
|
|
||||||
symbol. */
|
|
||||||
vTaskSwitchContext();
|
|
||||||
prvTaskExitError();
|
|
||||||
|
|
||||||
/* Should not get here! */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
void vPortEndScheduler( void )
|
|
||||||
{
|
|
||||||
/* Not implemented in ports where there is nothing to return to.
|
|
||||||
Artificially force an assert. */
|
|
||||||
configASSERT( uxCriticalNesting == 1000UL );
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
void vPortEnterCritical( void )
|
|
||||||
{
|
|
||||||
portDISABLE_INTERRUPTS();
|
|
||||||
uxCriticalNesting++;
|
|
||||||
|
|
||||||
/* This is not the interrupt safe version of the enter critical function so
|
|
||||||
assert() if it is being called from an interrupt context. Only API
|
|
||||||
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
||||||
the critical nesting count is 1 to protect against recursive calls if the
|
|
||||||
assert function also uses a critical section. */
|
|
||||||
if( uxCriticalNesting == 1 )
|
|
||||||
{
|
|
||||||
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
void vPortExitCritical( void )
|
|
||||||
{
|
|
||||||
configASSERT( uxCriticalNesting );
|
|
||||||
uxCriticalNesting--;
|
|
||||||
if( uxCriticalNesting == 0 )
|
|
||||||
{
|
|
||||||
portENABLE_INTERRUPTS();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
void xPortPendSVHandler( void )
|
|
||||||
{
|
|
||||||
/* This is a naked function. */
|
|
||||||
|
|
||||||
__asm volatile
|
|
||||||
(
|
|
||||||
" mrs r0, psp \n"
|
|
||||||
" isb \n"
|
|
||||||
" \n"
|
|
||||||
" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
|
|
||||||
" ldr r2, [r3] \n"
|
|
||||||
" \n"
|
|
||||||
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
|
|
||||||
" it eq \n"
|
|
||||||
" vstmdbeq r0!, {s16-s31} \n"
|
|
||||||
" \n"
|
|
||||||
" stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
|
|
||||||
" str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
|
|
||||||
" \n"
|
|
||||||
" stmdb sp!, {r0, r3} \n"
|
|
||||||
" mov r0, %0 \n"
|
|
||||||
" msr basepri, r0 \n"
|
|
||||||
" dsb \n"
|
|
||||||
" isb \n"
|
|
||||||
" bl vTaskSwitchContext \n"
|
|
||||||
" mov r0, #0 \n"
|
|
||||||
" msr basepri, r0 \n"
|
|
||||||
" ldmia sp!, {r0, r3} \n"
|
|
||||||
" \n"
|
|
||||||
" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
|
|
||||||
" ldr r0, [r1] \n"
|
|
||||||
" \n"
|
|
||||||
" ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
|
|
||||||
" \n"
|
|
||||||
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
|
|
||||||
" it eq \n"
|
|
||||||
" vldmiaeq r0!, {s16-s31} \n"
|
|
||||||
" \n"
|
|
||||||
" msr psp, r0 \n"
|
|
||||||
" isb \n"
|
|
||||||
" \n"
|
|
||||||
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
|
|
||||||
#if WORKAROUND_PMU_CM001 == 1
|
|
||||||
" push { r14 } \n"
|
|
||||||
" pop { pc } \n"
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
" \n"
|
|
||||||
" bx r14 \n"
|
|
||||||
" \n"
|
|
||||||
" .align 4 \n"
|
|
||||||
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
||||||
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
|
|
||||||
);
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
void xPortSysTickHandler( void )
|
|
||||||
{
|
|
||||||
/* The SysTick runs at the lowest interrupt priority, so when this interrupt
|
|
||||||
executes all interrupts must be unmasked. There is therefore no need to
|
|
||||||
save and then restore the interrupt mask value as its value is already
|
|
||||||
known. */
|
|
||||||
portDISABLE_INTERRUPTS();
|
|
||||||
{
|
|
||||||
/* Increment the RTOS tick. */
|
|
||||||
if( xTaskIncrementTick() != pdFALSE )
|
|
||||||
{
|
|
||||||
/* A context switch is required. Context switching is performed in
|
|
||||||
the PendSV interrupt. Pend the PendSV interrupt. */
|
|
||||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
portENABLE_INTERRUPTS();
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
#if( configUSE_TICKLESS_IDLE == 1 )
|
|
||||||
|
|
||||||
__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
|
|
||||||
{
|
|
||||||
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
|
|
||||||
TickType_t xModifiableIdleTime;
|
|
||||||
|
|
||||||
/* Make sure the SysTick reload value does not overflow the counter. */
|
|
||||||
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
|
|
||||||
{
|
|
||||||
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Stop the SysTick momentarily. The time the SysTick is stopped for
|
|
||||||
is accounted for as best it can be, but using the tickless mode will
|
|
||||||
inevitably result in some tiny drift of the time maintained by the
|
|
||||||
kernel with respect to calendar time. */
|
|
||||||
portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
|
|
||||||
|
|
||||||
/* Calculate the reload value required to wait xExpectedIdleTime
|
|
||||||
tick periods. -1 is used because this code will execute part way
|
|
||||||
through one of the tick periods. */
|
|
||||||
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
|
|
||||||
if( ulReloadValue > ulStoppedTimerCompensation )
|
|
||||||
{
|
|
||||||
ulReloadValue -= ulStoppedTimerCompensation;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enter a critical section but don't use the taskENTER_CRITICAL()
|
|
||||||
method as that will mask interrupts that should exit sleep mode. */
|
|
||||||
__asm volatile( "cpsid i" ::: "memory" );
|
|
||||||
__asm volatile( "dsb" );
|
|
||||||
__asm volatile( "isb" );
|
|
||||||
|
|
||||||
/* If a context switch is pending or a task is waiting for the scheduler
|
|
||||||
to be unsuspended then abandon the low power entry. */
|
|
||||||
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
|
|
||||||
{
|
|
||||||
/* Restart from whatever is left in the count register to complete
|
|
||||||
this tick period. */
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
|
||||||
|
|
||||||
/* Restart SysTick. */
|
|
||||||
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
|
||||||
|
|
||||||
/* Reset the reload register to the value required for normal tick
|
|
||||||
periods. */
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
|
||||||
|
|
||||||
/* Re-enable interrupts - see comments above the cpsid instruction()
|
|
||||||
above. */
|
|
||||||
__asm volatile( "cpsie i" ::: "memory" );
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Set the new reload value. */
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
|
|
||||||
|
|
||||||
/* Clear the SysTick count flag and set the count value back to
|
|
||||||
zero. */
|
|
||||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
||||||
|
|
||||||
/* Restart SysTick. */
|
|
||||||
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
|
||||||
|
|
||||||
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
|
|
||||||
set its parameter to 0 to indicate that its implementation contains
|
|
||||||
its own wait for interrupt or wait for event instruction, and so wfi
|
|
||||||
should not be executed again. However, the original expected idle
|
|
||||||
time variable must remain unmodified, so a copy is taken. */
|
|
||||||
xModifiableIdleTime = xExpectedIdleTime;
|
|
||||||
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
|
|
||||||
if( xModifiableIdleTime > 0 )
|
|
||||||
{
|
|
||||||
__asm volatile( "dsb" ::: "memory" );
|
|
||||||
__asm volatile( "wfi" );
|
|
||||||
__asm volatile( "isb" );
|
|
||||||
}
|
|
||||||
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
|
|
||||||
|
|
||||||
/* Re-enable interrupts to allow the interrupt that brought the MCU
|
|
||||||
out of sleep mode to execute immediately. see comments above
|
|
||||||
__disable_interrupt() call above. */
|
|
||||||
__asm volatile( "cpsie i" ::: "memory" );
|
|
||||||
__asm volatile( "dsb" );
|
|
||||||
__asm volatile( "isb" );
|
|
||||||
|
|
||||||
/* Disable interrupts again because the clock is about to be stopped
|
|
||||||
and interrupts that execute while the clock is stopped will increase
|
|
||||||
any slippage between the time maintained by the RTOS and calendar
|
|
||||||
time. */
|
|
||||||
__asm volatile( "cpsid i" ::: "memory" );
|
|
||||||
__asm volatile( "dsb" );
|
|
||||||
__asm volatile( "isb" );
|
|
||||||
|
|
||||||
/* Disable the SysTick clock without reading the
|
|
||||||
portNVIC_SYSTICK_CTRL_REG register to ensure the
|
|
||||||
portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
|
|
||||||
the time the SysTick is stopped for is accounted for as best it can
|
|
||||||
be, but using the tickless mode will inevitably result in some tiny
|
|
||||||
drift of the time maintained by the kernel with respect to calendar
|
|
||||||
time*/
|
|
||||||
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
|
|
||||||
|
|
||||||
/* Determine if the SysTick clock has already counted to zero and
|
|
||||||
been set back to the current reload value (the reload back being
|
|
||||||
correct for the entire expected idle time) or if the SysTick is yet
|
|
||||||
to count to zero (in which case an interrupt other than the SysTick
|
|
||||||
must have brought the system out of sleep mode). */
|
|
||||||
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
|
|
||||||
{
|
|
||||||
uint32_t ulCalculatedLoadValue;
|
|
||||||
|
|
||||||
/* The tick interrupt is already pending, and the SysTick count
|
|
||||||
reloaded with ulReloadValue. Reset the
|
|
||||||
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
|
|
||||||
period. */
|
|
||||||
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
|
|
||||||
|
|
||||||
/* Don't allow a tiny value, or values that have somehow
|
|
||||||
underflowed because the post sleep hook did something
|
|
||||||
that took too long. */
|
|
||||||
if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
|
|
||||||
{
|
|
||||||
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
|
|
||||||
}
|
|
||||||
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
|
|
||||||
|
|
||||||
/* As the pending tick will be processed as soon as this
|
|
||||||
function exits, the tick value maintained by the tick is stepped
|
|
||||||
forward by one less than the time spent waiting. */
|
|
||||||
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Something other than the tick interrupt ended the sleep.
|
|
||||||
Work out how long the sleep lasted rounded to complete tick
|
|
||||||
periods (not the ulReload value which accounted for part
|
|
||||||
ticks). */
|
|
||||||
ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
|
||||||
|
|
||||||
/* How many complete tick periods passed while the processor
|
|
||||||
was waiting? */
|
|
||||||
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
|
|
||||||
|
|
||||||
/* The reload value is set to whatever fraction of a single tick
|
|
||||||
period remains. */
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
|
|
||||||
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
|
|
||||||
value. */
|
|
||||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
||||||
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
|
||||||
vTaskStepTick( ulCompleteTickPeriods );
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
|
||||||
|
|
||||||
/* Exit with interrupts enabled. */
|
|
||||||
__asm volatile( "cpsie i" ::: "memory" );
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* #if configUSE_TICKLESS_IDLE */
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Setup the systick timer to generate the tick interrupts at the required
|
|
||||||
* frequency.
|
|
||||||
*/
|
|
||||||
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
|
|
||||||
{
|
|
||||||
/* Calculate the constants required to configure the tick interrupt. */
|
|
||||||
#if( configUSE_TICKLESS_IDLE == 1 )
|
|
||||||
{
|
|
||||||
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
|
|
||||||
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
|
|
||||||
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
|
||||||
}
|
|
||||||
#endif /* configUSE_TICKLESS_IDLE */
|
|
||||||
|
|
||||||
/* Stop and clear the SysTick. */
|
|
||||||
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
||||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
||||||
|
|
||||||
/* Configure SysTick to interrupt at the requested rate. */
|
|
||||||
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
||||||
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* This is a naked function. */
|
|
||||||
static void vPortEnableVFP( void )
|
|
||||||
{
|
|
||||||
__asm volatile
|
|
||||||
(
|
|
||||||
" ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
|
|
||||||
" ldr r1, [r0] \n"
|
|
||||||
" \n"
|
|
||||||
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
|
|
||||||
" str r1, [r0] \n"
|
|
||||||
" bx r14 "
|
|
||||||
);
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
#if( configASSERT_DEFINED == 1 )
|
|
||||||
|
|
||||||
void vPortValidateInterruptPriority( void )
|
|
||||||
{
|
|
||||||
uint32_t ulCurrentInterrupt;
|
|
||||||
uint8_t ucCurrentPriority;
|
|
||||||
|
|
||||||
/* Obtain the number of the currently executing interrupt. */
|
|
||||||
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
|
||||||
|
|
||||||
/* Is the interrupt number a user defined interrupt? */
|
|
||||||
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
||||||
{
|
|
||||||
/* Look up the interrupt's priority. */
|
|
||||||
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
||||||
|
|
||||||
/* The following assertion will fail if a service routine (ISR) for
|
|
||||||
an interrupt that has been assigned a priority above
|
|
||||||
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
|
||||||
function. ISR safe FreeRTOS API functions must *only* be called
|
|
||||||
from interrupts that have been assigned a priority at or below
|
|
||||||
configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
||||||
|
|
||||||
Numerically low interrupt priority numbers represent logically high
|
|
||||||
interrupt priorities, therefore the priority of the interrupt must
|
|
||||||
be set to a value equal to or numerically *higher* than
|
|
||||||
configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
||||||
|
|
||||||
Interrupts that use the FreeRTOS API must not be left at their
|
|
||||||
default priority of zero as that is the highest possible priority,
|
|
||||||
which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
|
|
||||||
and therefore also guaranteed to be invalid.
|
|
||||||
|
|
||||||
FreeRTOS maintains separate thread and ISR API functions to ensure
|
|
||||||
interrupt entry is as fast and simple as possible.
|
|
||||||
|
|
||||||
The following links provide detailed information:
|
|
||||||
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
|
||||||
http://www.freertos.org/FAQHelp.html */
|
|
||||||
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Priority grouping: The interrupt controller (NVIC) allows the bits
|
|
||||||
that define each interrupt's priority to be split between bits that
|
|
||||||
define the interrupt's pre-emption priority bits and bits that define
|
|
||||||
the interrupt's sub-priority. For simplicity all bits must be defined
|
|
||||||
to be pre-emption priority bits. The following assertion will fail if
|
|
||||||
this is not the case (if some bits represent a sub-priority).
|
|
||||||
|
|
||||||
If the application only uses CMSIS libraries for interrupt
|
|
||||||
configuration then the correct setting can be achieved on all Cortex-M
|
|
||||||
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
||||||
scheduler. Note however that some vendor specific peripheral libraries
|
|
||||||
assume a non-zero priority group setting, in which cases using a value
|
|
||||||
of zero will result in unpredictable behaviour. */
|
|
||||||
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* configASSERT_DEFINED */
|
|
||||||
|
|
||||||
|
|
||||||
@@ -1,243 +0,0 @@
|
|||||||
/*
|
|
||||||
* FreeRTOS Kernel V10.3.1
|
|
||||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
|
||||||
* this software and associated documentation files (the "Software"), to deal in
|
|
||||||
* the Software without restriction, including without limitation the rights to
|
|
||||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
|
||||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
|
||||||
* subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included in all
|
|
||||||
* copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
|
||||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
|
||||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
|
||||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* http://www.FreeRTOS.org
|
|
||||||
* http://aws.amazon.com/freertos
|
|
||||||
*
|
|
||||||
* 1 tab == 4 spaces!
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef PORTMACRO_H
|
|
||||||
#define PORTMACRO_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------
|
|
||||||
* Port specific definitions.
|
|
||||||
*
|
|
||||||
* The settings in this file configure FreeRTOS correctly for the
|
|
||||||
* given hardware and compiler.
|
|
||||||
*
|
|
||||||
* These settings should not be altered.
|
|
||||||
*-----------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Type definitions. */
|
|
||||||
#define portCHAR char
|
|
||||||
#define portFLOAT float
|
|
||||||
#define portDOUBLE double
|
|
||||||
#define portLONG long
|
|
||||||
#define portSHORT short
|
|
||||||
#define portSTACK_TYPE uint32_t
|
|
||||||
#define portBASE_TYPE long
|
|
||||||
|
|
||||||
typedef portSTACK_TYPE StackType_t;
|
|
||||||
typedef long BaseType_t;
|
|
||||||
typedef unsigned long UBaseType_t;
|
|
||||||
|
|
||||||
#if( configUSE_16_BIT_TICKS == 1 )
|
|
||||||
typedef uint16_t TickType_t;
|
|
||||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
|
||||||
#else
|
|
||||||
typedef uint32_t TickType_t;
|
|
||||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
|
||||||
|
|
||||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
|
||||||
not need to be guarded with a critical section. */
|
|
||||||
#define portTICK_TYPE_IS_ATOMIC 1
|
|
||||||
#endif
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Architecture specifics. */
|
|
||||||
#define portSTACK_GROWTH ( -1 )
|
|
||||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
|
||||||
#define portBYTE_ALIGNMENT 8
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Scheduler utilities. */
|
|
||||||
#define portYIELD() \
|
|
||||||
{ \
|
|
||||||
/* Set a PendSV to request a context switch. */ \
|
|
||||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
|
||||||
\
|
|
||||||
/* Barriers are normally not required but do ensure the code is completely \
|
|
||||||
within the specified behaviour for the architecture. */ \
|
|
||||||
__asm volatile( "dsb" ::: "memory" ); \
|
|
||||||
__asm volatile( "isb" ); \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
|
|
||||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
|
||||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
|
|
||||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Critical section management. */
|
|
||||||
extern void vPortEnterCritical( void );
|
|
||||||
extern void vPortExitCritical( void );
|
|
||||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
|
|
||||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
|
|
||||||
#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
|
|
||||||
#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)
|
|
||||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
|
||||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
|
||||||
not necessary for to use this port. They are defined so the common demo files
|
|
||||||
(which build with all the ports) will build. */
|
|
||||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
|
||||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Tickless idle/low power functionality. */
|
|
||||||
#ifndef portSUPPRESS_TICKS_AND_SLEEP
|
|
||||||
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
|
|
||||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
|
||||||
#endif
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Architecture specific optimisations. */
|
|
||||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
|
||||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
|
||||||
|
|
||||||
/* Generic helper function. */
|
|
||||||
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
|
|
||||||
{
|
|
||||||
uint8_t ucReturn;
|
|
||||||
|
|
||||||
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
|
||||||
return ucReturn;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check the configuration. */
|
|
||||||
#if( configMAX_PRIORITIES > 32 )
|
|
||||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Store/clear the ready priorities in a bit map. */
|
|
||||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
|
||||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
|
||||||
|
|
||||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
#ifdef configASSERT
|
|
||||||
void vPortValidateInterruptPriority( void );
|
|
||||||
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* portNOP() is not required by this port. */
|
|
||||||
#define portNOP()
|
|
||||||
|
|
||||||
#define portINLINE __inline
|
|
||||||
|
|
||||||
#ifndef portFORCE_INLINE
|
|
||||||
#define portFORCE_INLINE inline __attribute__(( always_inline))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
|
|
||||||
{
|
|
||||||
uint32_t ulCurrentInterrupt;
|
|
||||||
BaseType_t xReturn;
|
|
||||||
|
|
||||||
/* Obtain the number of the currently executing interrupt. */
|
|
||||||
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
|
||||||
|
|
||||||
if( ulCurrentInterrupt == 0 )
|
|
||||||
{
|
|
||||||
xReturn = pdFALSE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
xReturn = pdTRUE;
|
|
||||||
}
|
|
||||||
|
|
||||||
return xReturn;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
|
||||||
{
|
|
||||||
uint32_t ulNewBASEPRI;
|
|
||||||
|
|
||||||
__asm volatile
|
|
||||||
(
|
|
||||||
" mov %0, %1 \n" \
|
|
||||||
" msr basepri, %0 \n" \
|
|
||||||
" isb \n" \
|
|
||||||
" dsb \n" \
|
|
||||||
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
|
||||||
{
|
|
||||||
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
|
||||||
|
|
||||||
__asm volatile
|
|
||||||
(
|
|
||||||
" mrs %0, basepri \n" \
|
|
||||||
" mov %1, %2 \n" \
|
|
||||||
" msr basepri, %1 \n" \
|
|
||||||
" isb \n" \
|
|
||||||
" dsb \n" \
|
|
||||||
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
||||||
);
|
|
||||||
|
|
||||||
/* This return will not be reached but is necessary to prevent compiler
|
|
||||||
warnings. */
|
|
||||||
return ulOriginalBASEPRI;
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
|
||||||
{
|
|
||||||
__asm volatile
|
|
||||||
(
|
|
||||||
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
|
|
||||||
);
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* PORTMACRO_H */
|
|
||||||
|
|
||||||
@@ -500,7 +500,7 @@ void ui_SetPage_screen_init(void)
|
|||||||
ui_LabelAbout = lv_label_create(ui_PanelAbout);
|
ui_LabelAbout = lv_label_create(ui_PanelAbout);
|
||||||
lv_obj_set_width(ui_LabelAbout, LV_SIZE_CONTENT); /// 1
|
lv_obj_set_width(ui_LabelAbout, LV_SIZE_CONTENT); /// 1
|
||||||
lv_obj_set_height(ui_LabelAbout, LV_SIZE_CONTENT); /// 1
|
lv_obj_set_height(ui_LabelAbout, LV_SIZE_CONTENT); /// 1
|
||||||
lv_label_set_text(ui_LabelAbout, "About\nPower-Pico\nThe uA current meter\nV 1.0.8");
|
lv_label_set_text(ui_LabelAbout, "About\nPower-Pico\nThe uA current meter\nV 1.0.9");
|
||||||
lv_obj_set_style_text_font(ui_LabelAbout, &lv_font_montserrat_16, LV_PART_MAIN | LV_STATE_DEFAULT);
|
lv_obj_set_style_text_font(ui_LabelAbout, &lv_font_montserrat_16, LV_PART_MAIN | LV_STATE_DEFAULT);
|
||||||
|
|
||||||
// init setting values
|
// init setting values
|
||||||
|
|||||||
@@ -51,7 +51,7 @@ FREERTOS.IPParameters=Tasks01,configUSE_TICK_HOOK,FootprintOK
|
|||||||
FREERTOS.Tasks01=defaultTask,8,128,DefaultTask,Default,NULL,Dynamic,NULL,NULL
|
FREERTOS.Tasks01=defaultTask,8,128,DefaultTask,Default,NULL,Dynamic,NULL,NULL
|
||||||
FREERTOS.configUSE_TICK_HOOK=1
|
FREERTOS.configUSE_TICK_HOOK=1
|
||||||
File.Version=6
|
File.Version=6
|
||||||
GPIO.groupedBy=
|
GPIO.groupedBy=Group By Peripherals
|
||||||
KeepUserPlacement=false
|
KeepUserPlacement=false
|
||||||
Mcu.CPN=STM32F411CEU6
|
Mcu.CPN=STM32F411CEU6
|
||||||
Mcu.Family=STM32F4
|
Mcu.Family=STM32F4
|
||||||
@@ -143,6 +143,8 @@ PB0.Locked=true
|
|||||||
PB0.Signal=ADCx_IN8
|
PB0.Signal=ADCx_IN8
|
||||||
PB1.Locked=true
|
PB1.Locked=true
|
||||||
PB1.Signal=ADCx_IN9
|
PB1.Signal=ADCx_IN9
|
||||||
|
PB10.GPIOParameters=GPIO_PuPd
|
||||||
|
PB10.GPIO_PuPd=GPIO_PULLDOWN
|
||||||
PB10.Locked=true
|
PB10.Locked=true
|
||||||
PB10.Signal=GPIO_Output
|
PB10.Signal=GPIO_Output
|
||||||
PB13.Locked=true
|
PB13.Locked=true
|
||||||
@@ -194,7 +196,7 @@ ProjectManager.ProjectName=power_pico
|
|||||||
ProjectManager.ProjectStructure=
|
ProjectManager.ProjectStructure=
|
||||||
ProjectManager.RegisterCallBack=
|
ProjectManager.RegisterCallBack=
|
||||||
ProjectManager.StackSize=0x400
|
ProjectManager.StackSize=0x400
|
||||||
ProjectManager.TargetToolchain=CMake
|
ProjectManager.TargetToolchain=MDK-ARM V5.32
|
||||||
ProjectManager.ToolChainLocation=
|
ProjectManager.ToolChainLocation=
|
||||||
ProjectManager.UAScriptAfterPath=
|
ProjectManager.UAScriptAfterPath=
|
||||||
ProjectManager.UAScriptBeforePath=
|
ProjectManager.UAScriptBeforePath=
|
||||||
|
|||||||
Reference in New Issue
Block a user