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Power-Pico/Power_Pico/MDK-ARM/power_pico/stm32f4xx_hal_msp.o

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feat: first commit
2025-08-02 19:53:22 +08:00
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4(LI@<40>pG<70><47>pGO<47>0pGhI<>B<08>Hh!<21><>q`<60>!H<><48><EFBFBD><EFBFBD>pG @D8@@<10><><EFBFBD>F!hF<68><46><EFBFBD><EFBFBD>I h<>B<1C>H!hB<68><42>r`h<00><>p<05> H8hB<68>`h<00><05><> <00> <20><>iFH<><48><EFBFBD><EFBFBD><06><10> @D8@@ H<><48>hA<68><41>A`h<00><>@<00>HhA<68><41>Q`h"<00><>P<00>!<21><02><><EFBFBD><EFBFBD><EFBFBD>D8@hI<>B <09>Hh!<21><>A`O<> AH<><48><EFBFBD><EFBFBD>pG8@@8@@<10><><EFBFBD>F!hF<68><46><EFBFBD><EFBFBD>I h<>B!<21>H!hB<68><42>B`h<00><>@<05>H8hB<68>`h<00><05>O<EFBFBD> @<00> <20><> <03> <04>iFH<><48><EFBFBD><EFBFBD><06><10>8@@8@@<10><><EFBFBD>F!hF<68><46><EFBFBD><EFBFBD>#hL!H"<22>B<11>hC<68>`h<00><05>P<00><><EFBFBD>! <20><>iFH<12>L<>B<11>hC<68>`h<00><05>`<00><><EFBFBD>!<21><>iFH<><48><EFBFBD><EFBFBD><06><10>@08@@@@h
I<EFBFBD>B<07> Hh!<21>` <20><><EFBFBD><EFBFBD>I<>B<05>Hh!<21>`pG@D8@@<08>hI<>B<12>HhA<68>`h"<00><00>! <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>@ <20><><EFBFBD><EFBFBD>I<>B <09>HhA<68>`h<00><00><08>@D8@@hI<>B <09>Hh!<21> `O<><4F>QH<><48><EFBFBD><EFBFBD>pG@D8@@<10><><EFBFBD>F!hF<68><46><EFBFBD><EFBFBD>I h<>B!<21>H!hB<68> `h<00> <05>H8hB<68>`h<00><05>O<EFBFBD><4F>P<00> <20><> <03> <04>iFH<><48><EFBFBD><EFBFBD><06><10>@D8@@..\Core\Src\stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM__asm___19_stm32f4xx_hal_msp_c_d46e2bee____REV16X> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03>..\Core\Src\stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM__asm___19_stm32f4xx_hal_msp_c_d46e2bee____REVSHX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03>..\Core\Src\stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM__asm___19_stm32f4xx_hal_msp_c_d46e2bee____RRXX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03>&`<00><><EFBFBD><EFBFBD>armcc+|  
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  <07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>LA~<7E>T
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  <07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>nA~<7E><02>Axt~`<00><><EFBFBD><EFBFBD>armcc+|  
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  <07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>^A~<7E><02>Axl~`<00><><EFBFBD><EFBFBD>armcc+|  
  <07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08> <00>
../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM0../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM4?<3F>AHAL_MspInit4<16>Ytmpreg<10><02>x<16>4Ytmpreg<10><02>x\../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARMT?<3F>ZHAL_ADC_MspInitTihadc<10>:YGPIO_InitStruct?<02>`<16>*Ytmpreg<10><02>t<16>(PYtmpreg<10><02>t../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM?<3F>~HAL_ADC_MspDeInitihadc<10>`../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM^?<3F><01>HAL_SPI_MspInit^ihspi<10>:YGPIO_InitStruct?<02>`<16>*Ytmpreg<10><02>t<16>(ZYtmpreg<10><02>t../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM?<3F><01>HAL_SPI_MspDeInitihspi<10>L../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARML?<3F><01>HAL_TIM_PWM_MspInitLihtim_pwm<10>9<16>
6Ytmpreg<10><02>x<16>6JYtmpreg<10><02>xd../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARMn?<3F><01>HAL_TIM_MspPostInitnihtim<10>:YGPIO_InitStruct?<02>`<16>jYtmpreg<10><02>t<16>FfYtmpreg<10><02>t../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM,?<3F><01>HAL_TIM_PWM_MspDeInit,ihtim_pwm<10>`../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM^?<3F><01>HAL_UART_MspInit^ihuart<10>:YGPIO_InitStruct?<02>`<16>*Ytmpreg<10><02>t<16>(ZYtmpreg<10><02>t../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM?<3F><01>HAL_UART_MspDeInitihuart<10>@6 ../Core/Src/stm32f4xx_hal_msp.cp6 ../Core/Src/stm32f4xx_hal_msp.c<03>z|<01>6 ../Core/Src/stm32f4xx_hal_msp.c<03>$!l6 ../Core/Src/stm32f4xx_hal_msp.c<03><01>6 ../Core/Src/stm32f4xx_hal_msp.c<03>$!l6 ../Core/Src/stm32f4xx_hal_msp.c<03>%<01>6 ../Core/Src/stm32f4xx_hal_msp.c<03>~,<01>6 ../Core/Src/stm32f4xx_hal_msp.c<03>$v)6k|6 ../Core/Src/stm32f4xx_hal_msp.c<03>"<01>6 ../Core/Src/stm32f4xx_hal_msp.c<03>$!l6 ../Core/Src/stm32f4xx_hal_msp.c<03>%}0}04}}<00><>}R} RT}PPT}<00>P}<00><>}\} \^}PZT}<00>P}<00>*}*0}0L}P}<00><>}l} ln}PT,}<00>P}<00><>}\} \^}PZT}<00>P__DATE__ "Aug 2 2025"__TIME__ "19:37:32"__STDC__ 1__STDC_VERSION__ 199901L__STDC_HOSTED__ 1__STDC_ISO_10646__ 200607__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060960__TARGET_CPU_CORTEX_M4_FP_SP 1__TARGET_FPU_VFPV4_SP_D16 1__UVISION_VERSION 538_RTE_ 1STM32F411xE 1_RTE_ 1USE_HAL_DRIVER 1STM32F411xE 1__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_7E_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 4__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_MULTIPLY 1
../Drivers/CMSIS/Include/cmsis_version.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARMWXY__CMSIS_ARMCC_H ,__ARM_ARCH_7EM__ 15__ARM_FEATURE_DSP 1:__ASM __asm=__INLINE __inline@__STATIC_INLINE static __inlineC__STATIC_FORCEINLINE static __forceinlineF__NO_RETURN __declspec(noreturn)I__USED __attribute__((used))L__WEAK __attribute__((weak))O__PACKED __attribute__((packed))R__PACKED_STRUCT __packed structU__PACKED_UNION __packed unionX__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))[__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val))^__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))a__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val))d__UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))g__ALIGNED(x) __attribute__((aligned(x)))j__RESTRICT __restrictm__COMPILER_BARRIER() __memory_changed()s__PROGRAM_START __mainw__INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit{__STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base__VECTOR_TABLE __Vectors<01>__VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))<01>__NOP __nop<01>__WFI __wfi<01>__WFE __wfe<01>__SEV __sev<01>__ISB() __isb(0xF)<01>__DSB() __dsb(0xF)<01>__DMB() __dmb(0xF)<01>__REV __rev<01>__ROR __ror<01>__BKPT(value) __breakpoint(value)<01>__RBIT __rbit<01>__CLZ __clz<01>__LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")<01>__LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")<01>__LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")<01>__STREXB(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")<01>__STREXH(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")<01>__STREXW(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")<01>__CLREX __clrex<01>__SSAT __ssat<01>__USAT __usat<01>__LDRBT(ptr) ((uint8_t ) __ldrt(ptr))<01>__LDRHT(ptr) ((uint16_t) __ldrt(ptr))<01>__LDRT(ptr) ((uint32_t ) __ldrt(ptr))<01>__STRBT(value,ptr) __strt(value, ptr)<01>__STRHT(value,ptr) __strt(value, ptr)<01>__STRT(value,ptr) __strt(value, ptr)<01>__enable_fault_irq __enable_fiq<01>__disable_fault_irq __disable_fiq<01>__SADD8 __sadd8<01>__QADD8 __qadd8<01>__SHADD8 __shadd8<01>__UADD8 __uadd8<01>__UQADD8 __uqadd8<01>__UHADD8 __uhadd8<01>__SSUB8 __ssub8<01>__QSUB8 __qsub8<01>__SHSUB8 __shsub8<01>__USUB8 __usub8<01>__UQSUB8 __uqsub8<01>__UHSUB8 __uhsub8<01>__SADD16 __sadd16<01>__QADD16 __qadd16<01>__SHADD16 __shadd16<01>__UADD16 __uadd16<01>__UQADD16 __uqadd16<01>__UHADD16 __uhadd16<01>__SSUB16 __ssub16<01>__QSUB16 __qsub16<01>__SHSUB16 __shsub16<01>__USUB16 __usub16<01>__UQSUB16 __uqsub16<01>__UHSUB16 __uhsub16<01>__SASX __sasx<01>__QASX __qasx<01>__SHASX __shasx<01>__UASX __uasx<01>__UQASX __uqasx<01>__UHASX __uhasx<01>__SSAX __ssax<01>__QSAX __qsax<01>__SHSAX __shsax<01>__USAX __usax<01>__UQSAX __uqsax<01>__UHSAX __uhsax<01>__USAD8 __usad8<01>__USADA8 __usada8<01>__SSAT16 __ssat16<01>__USAT16 __usat16<01>__UXTB16 __uxtb16<01>__UXTAB16 __uxtab16<01>__SXTB16 __sxtb16<01>__SXTAB16 __sxtab16<01>__SMUAD __smuad<01>__SMUADX __smuadx<01>__SMLAD __smlad<01>__SMLADX __smladx<01>__SMLALD __smlald<01>__SMLALDX __smlaldx<01>__SMUSD __smusd<01>__SMUSDX __smusdx<01>__SMLSD __smlsd<01>__SMLSDX __smlsdx<01>__SMLSLD __smlsld<01>__SMLSLDX __smlsldx<01>__SEL __sel<01>__QADD __qadd<01>__QSUB __qsub<01>__PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )<01>__PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )<01>__SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U))<01>__SXTB16_RORn(ARG1,ARG2) __SXTB16(__ROR(ARG1, ARG2))
../Drivers/CMSIS/Include/cmsis_armcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM;<3B><01>__get_CONTROLga__resultgY__regControlgP<<3C><01>__set_CONTROL$gcontrolY__regControlgP;<3B><01>__get_IPSRga__resultgY__regIPSRgP;<3B><01>__get_APSRga__resultgY__regAPSRgP;<3B><01>__get_xPSRga__resultgY__regXPSRgP;<3B><01>__get_PSPga__resultgY__regProcessStackPointergP<<3C><01>__set_PSP$gtopOfProcStackY__regProcessStackPointergP;<3B><01>__get_MSPga__resultgY__regMainStackPointergP<<3C><01>__set_MSP$gtopOfMainStackY__regMainStackPointergP;<3B><01>__get_PRIMASKga__resultgY__regPriMaskgP<<3C><01>__set_PRIMASK$gpriMaskY__regPriMaskgP;<3B><01>__get_BASEPRIga__resultgY__regBasePrigP<<3C><01>__set_BASEPRI$gbasePriY__regBasePrigP<<3C><01>__set_BASEPRI_MAX$gbasePriY__regBasePriMaxgP;<3B> <01>__get_FAULTMASKga__resultgY__regFaultMaskgP<<3C> <01>__set_FAULTMASK$gfaultMaskY__regFaultMaskgP;<3B>
<01>__get_FPSCRga__resultgY__regfpscrgP<<3C>
<01>__set_FPSCR$gfpscrY__regfpscrgP[\]__CMSIS_COMPILER_H "<00><00> ../Drivers/CMSIS/Include/E:\Program Files\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.hstdint.hcmsis_armcc.h<01>
../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM_`a ARM_MPU_ARMV7_H "ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)#ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)$ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)%ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)&ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)'ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)(ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU))ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)*ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)+ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU),ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)-ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU).ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)/ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)0ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)1ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)2ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)3ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)4ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)5ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)6ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)7ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)8ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)9ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU):ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU);ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)<ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)=ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)?ARM_MPU_AP_NONE 0U@ARM_MPU_AP_PRIV 1UAARM_MPU_AP_URO 2UBARM_MPU_AP_FULL 3UCARM_MPU_AP_PRO 5UDARM_MPU_AP_RO 6UKARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk))XARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))gARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | (((MPU_RASR_ENABLE_Msk)))){ARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)<01>ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)<01>ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))<01>ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))<01>ARM_MPU_CACHEP_NOCACHE 0U<01>ARM_MPU_CACHEP_WB_WRA 1U<01>ARM_MPU_CACHEP_WT_NWA 2U<01>ARM_MPU_CACHEP_WB_NWA 3UH< ../Drivers/CMSIS/Include/mpu_armv7.h<01>
../Drivers/CMSIS/Include/mpu_armv7.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>RBARg#RASRg#PARM_MPU_Region_t<12><01><<3C><01>ARM_MPU_Enable$gMPU_Control<<3C><01>ARM_MPU_Disable<<3C><01>ARM_MPU_ClrRegion$grnr<<3C><01>ARM_MPU_SetRegion$grbar$grasr<<3C><01>ARM_MPU_SetRegionEx$grnr$grbar$grasr<<3C><01>ARM_MPU_OrderedMemcpy$2dst$@src$glen\igtg",g"6#<<<3C><01>ARM_MPU_Load$<12>table$gcntsrowWordSize6 <12>"<12>cdef __CORE_CM4_H_GENERIC "?B__CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)D__CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB )G__CORTEX_M (4U)O__FPU_USED 1U<03><01>__CORE_CM4_H_DEPENDANT <01>__I volatile const<01>__O volatile<01>__IO volatile<01>__IM volatile const<01>__OM volatile<01>__IOM volatile<01>APSR_N_Pos 31U<01>APSR_N_Msk (1UL << APSR_N_Pos)<01>APSR_Z_Pos 30U<01>APSR_Z_Msk (1UL << APSR_Z_Pos)<01>APSR_C_Pos 29U<01>APSR_C_Msk (1UL << APSR_C_Pos)<01>APSR_V_Pos 28U<01>APSR_V_Msk (1UL << APSR_V_Pos)<01>APSR_Q_Pos 27U<01>APSR_Q_Msk (1UL << APSR_Q_Pos)<01>APSR_GE_Pos 16U<01>APSR_GE_Msk (0xFUL << APSR_GE_Pos)<01>IPSR_ISR_Pos 0U<01>IPSR_ISR_Msk (0x1FFUL )<01>xPSR_N_Pos 31U<01>xPSR_N_Msk (1UL << xPSR_N_Pos)<01>xPSR_Z_Pos 30U<01>xPSR_Z_Msk (1UL << xPSR_Z_Pos)<01>xPSR_C_Pos 29U<01>xPSR_C_Msk (1UL << xPSR_C_Pos)<01>xPSR_V_Pos 28U<01>xPSR_V_Msk (1UL << xPSR_V_Pos)<01>xPSR_Q_Pos 27U<01>xPSR_Q_Msk (1UL << xPSR_Q_Pos)<01>xPSR_ICI_IT_2_Pos 25U<01>xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)<01>xPSR_T_Pos 24U<01>xPSR_T_Msk (1UL << xPSR_T_Pos)<01>xPSR_GE_Pos 16U<01>xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)<01>xPSR_ICI_IT_1_Pos 10U<01>xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)<01>xPSR_ISR_Pos 0U<01>xPSR_ISR_Msk (0x1FFUL )<01>CONTROL_FPCA_Pos 2U<01>CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)<01>CONTROL_SPSEL_Pos 1U<01>CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)<01>CONTROL_nPRIV_Pos 0U<01>CONTROL_nPRIV_Msk (1UL )<01>NVIC_STIR_INTID_Pos 0U<01>NVIC_STIR_INTID_Msk (0x1FFUL )<01>SCB_CPUID_IMPLEMENTER_Pos 24U<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)<01>SCB_CPUID_VARIANT_Pos 20U<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)<01>SCB_CPUID_ARCHITECTURE_Pos 16U<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)<01>SCB_CPUID_PARTNO_Pos 4U<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)<01>SCB_CPUID_REVISION_Pos 0U<01>SCB_CPUID_REVISION_Msk (0xFUL )<01>SCB_ICSR_NMIPENDSET_Pos 31U<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)<01>SCB_ICSR_PENDSVSET_Pos 28U<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)<01>SCB_ICSR_PENDSVCLR_Pos 27U<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)<01>SCB_ICSR_PENDSTSET_Pos 26U<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)<01>SCB_ICSR_PENDSTCLR_Pos 25U<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)<01>SCB_ICSR_ISRPREEMPT_Pos 23U<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)<01>SCB_ICSR_ISRPENDING_Pos 22U<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)<01>SCB_ICSR_VECTPENDING_Pos 12U<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)<01>SCB_ICSR_RETTOBASE_Pos 11U<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)<01>SCB_ICSR_VECTACTIVE_Pos 0U<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )<01>SCB_VTOR_TBLOFF_Pos 7U<01>SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)<01>SCB_AIRCR_VECTKEY_Pos 16U<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)<01>SCB_AIRCR_VECTKEYSTAT_Pos 16U<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)<01>SCB_AIRCR_ENDIANESS_Pos 15U<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)<01>SCB_AIRCR_PRIGROUP_Pos 8U<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)<01>SCB_AIRCR_SYSRESETREQ_Pos 2U<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_
MPU_RASR_C_Pos 17U<01>
MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)<01>
MPU_RASR_B_Pos 16U<01>
MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)<01>
MPU_RASR_SRD_Pos 8U<01>
MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)<01>
MPU_RASR_SIZE_Pos 1U<01>
MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)<01>
MPU_RASR_ENABLE_Pos 0U<01>
MPU_RASR_ENABLE_Msk (1UL )<01>
FPU_FPCCR_ASPEN_Pos 31U<01>
FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)<01>
FPU_FPCCR_LSPEN_Pos 30U<01>
FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)<01>
FPU_FPCCR_MONRDY_Pos 8U<01>
FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)<01>
FPU_FPCCR_BFRDY_Pos 6U<01>
FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)<01>
FPU_FPCCR_MMRDY_Pos 5U<01>
FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)<01>
FPU_FPCCR_HFRDY_Pos 4U<01>
FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)<01>
FPU_FPCCR_THREAD_Pos 3U<01>
FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)<01>
FPU_FPCCR_USER_Pos 1U<01>
FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)<01>
FPU_FPCCR_LSPACT_Pos 0U<01>
FPU_FPCCR_LSPACT_Msk (1UL )<01>
FPU_FPCAR_ADDRESS_Pos 3U<01>
FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)<01>
FPU_FPDSCR_AHP_Pos 26U<01>
FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)<01>
FPU_FPDSCR_DN_Pos 25U<01>
FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)<01>
FPU_FPDSCR_FZ_Pos 24U<01>
FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)<01>
FPU_FPDSCR_RMode_Pos 22U<01>
FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)<01>
FPU_MVFR0_FP_rounding_modes_Pos 28U<01>
FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)<01>
FPU_MVFR0_Short_vectors_Pos 24U<01>
FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)<01>
FPU_MVFR0_Square_root_Pos 20U<01>
FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)<01>
FPU_MVFR0_Divide_Pos 16U<01>
FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)<01>
FPU_MVFR0_FP_excep_trapping_Pos 12U<01>
FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)<01>
FPU_MVFR0_Double_precision_Pos 8U<01>
FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)<01>
FPU_MVFR0_Single_precision_Pos 4U<01>
FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)<01>
FPU_MVFR0_A_SIMD_registers_Pos 0U<01>
FPU_MVFR0_A_SIMD_registers_Msk (0xFUL )<01>
FPU_MVFR1_FP_fused_MAC_Pos 28U<01>
FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)<01>
FPU_MVFR1_FP_HPFP_Pos 24U<01>
FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)<01>
FPU_MVFR1_D_NaN_mode_Pos 4U<01>
FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)<01>
FPU_MVFR1_FtZ_mode_Pos 0U<01>
FPU_MVFR1_FtZ_mode_Msk (0xFUL )<01>
FPU_MVFR2_VFP_Misc_Pos 4U<01>
FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)<01> CoreDebug_DHCSR_DBGKEY_Pos 16U<01> CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)<01> CoreDebug_DHCSR_S_RESET_ST_Pos 25U<01> CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)<01> CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U<01> CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)<01> CoreDebug_DHCSR_S_LOCKUP_Pos 19U<01> CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)<01> CoreDebug_DHCSR_S_SLEEP_Pos 18U<01> CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)<01> CoreDebug_DHCSR_S_HALT_Pos 17U<01> CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)<01> CoreDebug_DHCSR_S_REGRDY_Pos 16U<01> CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)<01> CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U<01> CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)<01> CoreDebug_DHCSR_C_MASKINTS_Pos 3U<01> CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)<01> CoreDebug_DHCSR_C_STEP_Pos 2U<01> CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)<01> CoreDebug_DHCSR_C_HALT_Pos 1U<01> CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)<01> CoreDebug_DHCSR_C_DEBUGEN_Pos 0U<01> CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )<01> CoreDebug_DCRSR_REGWnR_Pos 16U<01> CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)<01> CoreDebug_DCRSR_REGSEL_Pos 0U<01> CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )<01> CoreDebug_DEMCR_TRCENA_Pos 24U<01> CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)<01> CoreDebug_DEMCR_MON_REQ_Pos 19U<01> CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)<01> CoreDebug_DEMCR_MON_STEP_Pos 18U<01> CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)<01> CoreDebug_DEMCR_MON_PEND_Pos 17U<01> CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)<01> CoreDebug_DEMCR_MON_EN_Pos 16U<01> CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)<01> CoreDebug_DEMCR_VC_HARDERR_Pos 10U<01> CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)<01> CoreDebug_DEMCR_VC_INTERR_Pos 9U<01> CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)<01> CoreDebug_DEMCR_VC_BUSERR_Pos 8U<01> CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)<01> CoreDebug_DEMCR_VC_STATERR_Pos 7U<01> CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)<01> CoreDebug_DEMCR_VC_CHKERR_Pos 6U<01> CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)<01> CoreDebug_DEMCR_VC_NOCPERR_Pos 5U<01> CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)<01> CoreDebug_DEMCR_VC_MMERR_Pos 4U<01> CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)<01> CoreDebug_DEMCR_VC_CORERESET_Pos 0U<01> CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )<01> _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)<01> _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)<01> SCS_BASE (0xE000E000UL)<01> ITM_BASE (0xE0000000UL)<01> DWT_BASE (0xE0001000UL)<01> TPI_BASE (0xE0040000UL)<01> CoreDebug_BASE (0xE000EDF0UL)<01> SysTick_BASE (SCS_BASE + 0x0010UL)<01> NVIC_BASE (SCS_BASE + 0x0100UL)<01> SCB_BASE (SCS_BASE + 0x0D00UL)<01> SCnSCB ((SCnSCB_Type *) SCS_BASE )<01> SCB ((SCB_Type *) SCB_BASE )<01> SysTick ((SysTick_Type *) SysTick_BASE )<01> NVIC ((NVIC_Type *) NVIC_BASE )<01> ITM ((ITM_Type *) ITM_BASE )<01> DWT ((DWT_Type *) DWT_BASE )<01> TPI ((TPI_Type *) TPI_BASE )<01> CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)<01> MPU_BASE (SCS_BASE + 0x0D90UL)<01> MPU ((MPU_Type *) MPU_BASE )<01> FPU_BASE (SCS_BASE + 0x0F30UL)<01> FPU ((FPU_Type *) FPU_BASE )<01> NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping<01> NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping<01> NVIC_EnableIRQ __NVIC_EnableIRQ<01> NVIC_GetEnableIRQ __NVIC_GetEnableIRQ<01> NVIC_DisableIRQ __NVIC_DisableIRQ<01> NVIC_GetPendingIRQ __NVIC_GetPendingIRQ<01> NVIC_SetPendingIRQ __NVIC_SetPendingIRQ<01> NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ<01> NVIC_GetActive __NVIC_GetActive<01> NVIC_SetPriority __NVIC_SetPrio
../Drivers/CMSIS/Include/core_cm4.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>!_reserved0g#!GEg# !_reserved1g#!Qg#!Vg#!Cg#!Zg#!Ng#S<>b<12>wgPAPSR_Typeb<01>*<2A>!ISRg# !_reserved0g#S<>b<12>wgPIPSR_Type<12><01>*<2A>!ISRg# !_reserved0g#!ICI_IT_1g#!GEg# !_reserved1g#!Tg#!ICI_IT_2g#!Qg#!Vg#!Cg#!Zg#!Ng#S<>b<12>wgPxPSR_Type<12><01>*<2A>!nPRIVg#!SPSELg#!FPCAg#!_reserved0g#S<>b<12>wgPCONTROL_Type<01>*<2A> <09><03><12>ISERK#<03>gRESERVED0`# <03><12>ICER|#<23><03>gRESERVED1<12>#<23><03><12>ISPR<12>#<23><03>gRESERVED2<12>#<23><03><12>ICPR<12>#<23><03>gRESERVED3<12>#<23><03><12>IABR#<23><03>g7RESERVED4+#<23><03><12><01>IPH#<23><03>g<01>RESERVED5]#<23>STIR<12>#<23>tgtHPNVIC_TypeF<01>*<2A> <0B>CPUID<12>#ICSR<12>#VTOR<12>#AIRCR<12># SCR<12>#CCR<12>#<03> <12> SHP<12>#SHCSR<12>#$CFSR<12>#(HFSR<12>#,DFSR<12>#0MMFAR<12>#4BFAR<12>#8AFSR<12>#<<03>
<12>PFR^#@DFR<12>#HADR<12>#L<03> <12>MMFR<12>#P<03> <12>ISAR<12>#`<03> gRESERVED0<12>#tCPACR<12>#<23>gt<12>PSCB_Type<12><01>*<2A> <03> gRESERVED0<12>#ICTR<12>#ACTLR<12>#PSCnSCB_Type<12><01>*<2A> CTRL<12>#LOAD<12>#VAL<12>#CALIB<12># PSysTick_TypeF<01>S<> u8<12>u16<12>u32<12>tW*<2A><10> <03> TPORT<12>#<03> g<01>RESERVED0<12>#<23>TER<12>#<23><03>gRESERVED1<12>#<23>TPR<12>#<23><03>gRESERVED2#<23>TCR<12>#<23><03>gRESERVED3H#<23><03>g*RESERVED4e#<23>LAR<12>#<23>LSR<12>#<23><03>gRESERVED5<12>#<23>PID4<12>#<23>PID5<12>#<23>PID6<12>#<23>PID7<12>#<23>PID0<12>#<23>PID1<12>#<23>PID2<12>#<23>PID3<12>#<23>CID0<12>#<23>CID1<12>#<23>CID2<12>#<23>CID3<12>#<23>t<12>PITM_Type<12><01>*<2A>\CTRL<12>#CYCCNT<12>#CPICNT<12>#EXCCNT<12># SLEEPCNT<12>#LSUCNT<12>#FOLDCNT<12>#PCSR<12>#COMP0<12># MASK0<12>#$FUNCTION0<12>#(<03>gRESERVED0 #,COMP1<12>#0MASK1<12>#4FUNCTION1<12>#8<03>gRESERVED1N #<COMP2<12>#@MASK2<12>#DFUNCTION2<12>#H<03>gRESERVED2<12> #LCOMP3<12>#PMASK3<12>#TFUNCTION3<12>#XPDWT_Typei<01>*<2A><17>SSPSR<12>#CSPSR<12>#<03>gRESERVED0
#ACPR<12>#<03>g6RESERVED15
#SPPR<12>#<23><03>g<01>RESERVED2^
#<23>FFSR<12>#<23>FFCR<12>#<23>FSCR<12>#<23><03>g<01>RESERVED3<12>
#<23>TRIGGER<12>#<23>FIFO0<12>#<23>ITATBCTR2<12>#<23><03>gRESERVED4<12>
#<23>ITATBCTR0<12>#<23>FIFO1<12>#<23>ITCTRL<12>#<23><03>g&RESERVED5= #<23>CLAIMSET<12>#<23>CLAIMCLR<12>#<23><03>gRESERVED7| #<23>DEVID<12>#<23>DEVTYPE<12>#<23>PTPI_Type<12> <01>*<2A>,TYPE<12>#CTRL<12>#RNR<12>#RBAR<12># RASR<12>#RBAR_A1<12>#RASR_A1<12>#RBAR_A2<12>#RASR_A2<12># RBAR_A3<12>#$RASR_A3<12>#(PMPU_Type<12> <01> *<2A><03>gRESERVED0x #FPCCR<12>#FPCAR<12>#FPDSCR<12># MVFR0<12>#MVFR1<12>#MVFR2<12>#PFPU_Typet <01>
*<2A>DHCSR<12>#DCRSR<12>#DCRDR<12>#DEMCR<12># PCoreDebug_Type<12> <01> t*qITM_RxBufferE <<3C><01> __NVIC_SetPriorityGrouping$gPriorityGroup\reg_valueg\PriorityGroupTmpg;<3B><01> __NVIC_GetPriorityGroupingga__resultg<<3C><01> __NVIC_EnableIRQ$IRQn;<3B><01> __NVIC_GetEnableIRQg$IRQna__resultg<<3C><01> __NVIC_DisableIRQ$IRQn;<3B><01> __NVIC_GetPendingIRQg$IRQna__resultg<<3C><01> __NVIC_SetPendingIRQ$IRQn<<3C><01> __NVIC_ClearPendingIRQ$IRQn;<3B><01>__NVIC_GetActiveg$IRQna__resultg<<3C><01>__NVIC_SetPriority$IRQn$gpriority;<3B><01>__NVIC_GetPriorityg$IRQna__resultg;<3B> <01>NVIC_EncodePriorityg$gPriorityGroup$gPreemptPriority$gSubPrioritya__resultg\PriorityGroupTmpg\PreemptPriorityBitsg\SubPriorityBitsg<<3C>"<01>NVIC_DecodePriority$gPriority$gPriorityGroup$$pPreemptPriority$$pSubPriority\PriorityGroupTmpg\PreemptPriorityBitsg\SubPriorityBitsg"g<<3C>"<01>__NVIC_SetVector$IRQn$gvector\vectors;<3B>#<01>__NVIC_GetVectorg$IRQna__resultg\vectors<<3C>#<01>"__NVIC_SystemReset;<3B>$<01>SCB_GetFPUTypega__resultg\mvfr0g;<3B>$<01>SysTick_Configg$gticksa__resultg;<3B>$<01>ITM_SendCharg$gcha__resultg;<3B>%<01>ITM_ReceiveChar*a__result*\ch*;<3B>%<01>ITM_CheckChar*a__result*<00>K ITM_RxBufferhijk__SYSTEM_STM32F4XX_H `W ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.hL
../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARMqSystemCoreClockgH<03>qAHBPrescTable<03>qAPBPrescTable1FP<00>SystemCoreClockAHBPrescTable:APBPrescTablemno"__STM32F411xE_H /__CM4_REV 0x0001U0__MPU_PRESENT 1U1__NVIC_PRIO_BITS 4U2__Vendor_SysTickConfig 0U3__FPU_PRESENT 1U<03><03><03><01>FLASH_BASE 0x08000000UL<01>SRAM1_BASE 0x20000000UL<01>PERIPH_BASE 0x40000000UL<01>SRAM1_BB_BASE 0x22000000UL<01>PERIPH_BB_BASE 0x42000000UL<01>BKPSRAM_BB_BASE 0x42480000UL<01>FLASH_END 0x0807FFFFUL<01>FLASH_OTP_BASE 0x1FFF7800UL<01>FLASH_OTP_END 0x1FFF7A0FUL<01>SRAM_BASE SRAM1_BASE<01>SRAM_BB_BASE SRAM1_BB_BASE<01>APB1PERIPH_BASE PERIPH_BASE<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)<01>AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)<01>AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)<01>TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)<01>TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)<01>TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)<01>TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)<01>RTC_BASE (APB1PERIPH_BASE + 0x2800UL)<01>WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)<01>IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)<01>I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)<01>SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)<01>SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)<01>I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)<01>USART2_BASE (APB1PERIPH_BASE + 0x4400UL)<01>I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)<01>I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)<01>I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)<01>PWR_BASE (APB1PERIPH_BASE + 0x7000UL)<01>TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)<01>USART1_BASE (APB2PERIPH_BASE + 0x1000UL)<01>USART6_BASE (APB2PERIPH_BASE + 0x1400UL)<01>ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)<01>ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)<01>ADC_BASE ADC1_COMMON_BASE<01>SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)<01>SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)<01>SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)<01>SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)<01>EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)<01>TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)<01>TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)<01>TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)<01>SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)<01>GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)<01>GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)<01>GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)<01>GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)<01>GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)<01>GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)<01>CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)<01>RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)<01>FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)<01>DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)<01>DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)<01>DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)<01>DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)<01>DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)<01>DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)<01>DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)<01>DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)<01>DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)<01>DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)<01>DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)<01>DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)<01>DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)<01>DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)<01>DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)<01>DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)<01>DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)<01>DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)<01>DBGMCU_BASE 0xE0042000UL<01>USB_OTG_FS_PERIPH_BASE 0x50000000UL<01>USB_OTG_GLOBAL_BASE 0x000UL<01>USB_OTG_DEVICE_BASE 0x800UL<01>USB_OTG_IN_ENDPOINT_BASE 0x900UL<01>USB_OTG_OUT_ENDPOINT_BASE 0xB00UL<01>USB_OTG_EP_REG_SIZE 0x20UL<01>USB_OTG_HOST_BASE 0x400UL<01>USB_OTG_HOST_PORT_BASE 0x440UL<01>USB_OTG_HOST_CHANNEL_BASE 0x500UL<01>USB_OTG_HOST_CHANNEL_SIZE 0x20UL<01>USB_OTG_PCGCCTL_BASE 0xE00UL<01>USB_OTG_FIFO_BASE 0x1000UL<01>USB_OTG_FIFO_SIZE 0x1000UL<01>UID_BASE 0x1FFF7A10UL<01>FLASHSIZE_BASE 0x1FFF7A22UL<01>PACKAGE_BASE 0x1FFF7BF0UL<01>TIM2 ((TIM_TypeDef *) TIM2_B
ADC_JSQR_JSQ4_Pos (15U)<01>
ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)<01>
ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk<01>
ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)<01>
ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)<01>
ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)<01>
ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)<01>
ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)<01>
ADC_JSQR_JL_Pos (20U)<01>
ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)<01>
ADC_JSQR_JL ADC_JSQR_JL_Msk<01>
ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)<01>
ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)<01>
ADC_JDR1_JDATA_Pos (0U)<01>
ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)<01>
ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk<01>
ADC_JDR2_JDATA_Pos (0U)<01>
ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)<01>
ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk<01>
ADC_JDR3_JDATA_Pos (0U)<01>
ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)<01>
ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk<01>
ADC_JDR4_JDATA_Pos (0U)<01>
ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)<01>
ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk<01>
ADC_DR_DATA_Pos (0U)<01>
ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)<01>
ADC_DR_DATA ADC_DR_DATA_Msk<01>
ADC_DR_ADC2DATA_Pos (16U)<01>
ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)<01>
ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk<01>
ADC_CSR_AWD1_Pos (0U)<01>
ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)<01>
ADC_CSR_AWD1 ADC_CSR_AWD1_Msk<01>
ADC_CSR_EOC1_Pos (1U)<01>
ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)<01>
ADC_CSR_EOC1 ADC_CSR_EOC1_Msk<01>
ADC_CSR_JEOC1_Pos (2U)<01>
ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)<01>
ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk<01>
ADC_CSR_JSTRT1_Pos (3U)<01>
ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)<01>
ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk<01>
ADC_CSR_STRT1_Pos (4U)<01>
ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)<01>
ADC_CSR_STRT1 ADC_CSR_STRT1_Msk<01>
ADC_CSR_OVR1_Pos (5U)<01>
ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)<01>
ADC_CSR_OVR1 ADC_CSR_OVR1_Msk<01>
ADC_CSR_DOVR1 ADC_CSR_OVR1<01>
ADC_CCR_MULTI_Pos (0U)<01>
ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)<01>
ADC_CCR_MULTI ADC_CCR_MULTI_Msk<01>
ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)<01>
ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)<01>
ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)<01>
ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)<01>
ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)<01>
ADC_CCR_DELAY_Pos (8U)<01>
ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)<01>
ADC_CCR_DELAY ADC_CCR_DELAY_Msk<01>
ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)<01>
ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)<01>
ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)<01>
ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)<01>
ADC_CCR_DDS_Pos (13U)<01>
ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)<01>
ADC_CCR_DDS ADC_CCR_DDS_Msk<01>
ADC_CCR_DMA_Pos (14U)<01>
ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)<01>
ADC_CCR_DMA ADC_CCR_DMA_Msk<01>
ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)<01>
ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)<01>
ADC_CCR_ADCPRE_Pos (16U)<01>
ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)<01>
ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk<01>
ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)<01>
ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)<01>
ADC_CCR_VBATE_Pos (22U)<01>
ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)<01>
ADC_CCR_VBATE ADC_CCR_VBATE_Msk<01>
ADC_CCR_TSVREFE_Pos (23U)<01>
ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)<01>
ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk<01>
ADC_CDR_DATA1_Pos (0U)<01>
ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)<01>
ADC_CDR_DATA1 ADC_CDR_DATA1_Msk<01>
ADC_CDR_DATA2_Pos (16U)<01>
ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)<01>
ADC_CDR_DATA2 ADC_CDR_DATA2_Msk<01>
ADC_CDR_RDATA_MST ADC_CDR_DATA1<01>
ADC_CDR_RDATA_SLV ADC_CDR_DATA2<01>
CRC_DR_DR_Pos (0U)<01>
CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)<01>
CRC_DR_DR CRC_DR_DR_Msk<01>
CRC_IDR_IDR_Pos (0U)<01>
CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)<01>
CRC_IDR_IDR CRC_IDR_IDR_Msk<01> CRC_CR_RESET_Pos (0U)<01> CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)<01> CRC_CR_RESET CRC_CR_RESET_Msk<01> DMA_SxCR_CHSEL_Pos (25U)<01> DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)<01> DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk<01> DMA_SxCR_CHSEL_0 0x02000000U<01> DMA_SxCR_CHSEL_1 0x04000000U<01> DMA_SxCR_CHSEL_2 0x08000000U<01> DMA_SxCR_MBURST_Pos (23U)<01> DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)<01> DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk<01> DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)<01> DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)<01> DMA_SxCR_PBURST_Pos (21U)<01> DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)<01> DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk<01> DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)<01> DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)<01> DMA_SxCR_CT_Pos (19U)<01> DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)<01> DMA_SxCR_CT DMA_SxCR_CT_Msk<01> DMA_SxCR_DBM_Pos (18U)<01> DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)<01> DMA_SxCR_DBM DMA_SxCR_DBM_Msk<01> DMA_SxCR_PL_Pos (16U)<01> DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)<01> DMA_SxCR_PL DMA_SxCR_PL_Msk<01> DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)<01> DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)<01> DMA_SxCR_PINCOS_Pos (15U)<01> DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)<01> DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk<01> DMA_SxCR_MSIZE_Pos (13U)<01> DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)<01> DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk<01> DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)<01> DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)<01> DMA_SxCR_PSIZE_Pos (11U)<01> DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)<01> DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk<01> DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)<01> DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)<01> DMA_SxCR_MINC_Pos (10U)<01> DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)<01> DMA_SxCR_MINC DMA_SxCR_MINC_Msk<01> DMA_SxCR_PINC_Pos (9U)<01> DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)<01> DMA_SxCR_PINC DMA_SxCR_PINC_Msk<01> DMA_SxCR_CIRC_Pos (8U)<01> DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)<01> DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk<01> DMA_SxCR_DIR_Pos (6U)<01> DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)<01> DMA_SxCR_DIR DMA_SxCR_DIR_Msk<01> DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)<01> DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)<01> DMA_SxCR_PFCTRL_Pos (5U)<01> DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)<01> DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk<01> DMA_SxCR_TCIE_Pos (4U)<01> DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)<01> DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk<01> DMA_SxCR_HTIE_Pos (3U)<01> DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)<01> DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk<01> DMA_SxCR_TEIE_Pos (2U)<01> DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)<01> DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk<01> DMA_SxCR_DMEIE_Pos (1U)<01> DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)<01> DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk<01> DMA_SxCR_EN_Pos (0U)<01> DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)<01> DMA_SxCR_EN DMA_SxCR_EN_Msk<01> DMA_SxCR_ACK_Pos (20U)<01> DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)<01> DMA_SxCR_ACK DMA_SxCR_ACK_Msk<01> DMA_SxNDT_Pos (0U)<01> DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)<01> DMA_SxNDT DMA_SxNDT_Msk<01> DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)<01> DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)<01> DMA_SxFCR_FEIE_Pos (7U)<01> DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)<01> DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk<01> DMA_SxFCR_FS_Pos (3U)<01> DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)<01> DMA_SxFCR_FS DMA_SxFCR_FS_Msk<01> DMA_SxFCR_FS_0 (0x
../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>
NonMaskableInt_IRQnrMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQnTAMP_STAMP_IRQnRTC_WKUP_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQn EXTI4_IRQn
DMA1_Stream0_IRQn DMA1_Stream1_IRQn DMA1_Stream2_IRQn DMA1_Stream3_IRQnDMA1_Stream4_IRQnDMA1_Stream5_IRQnDMA1_Stream6_IRQnADC_IRQnEXTI9_5_IRQnTIM1_BRK_TIM9_IRQnTIM1_UP_TIM10_IRQnTIM1_TRG_COM_TIM11_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&EXTI15_10_IRQn(RTC_Alarm_IRQn)OTG_FS_WKUP_IRQn*DMA1_Stream7_IRQn/SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3DMA2_Stream0_IRQn8DMA2_Stream1_IRQn9DMA2_Stream2_IRQn:DMA2_Stream3_IRQn;DMA2_Stream4_IRQn<OTG_FS_IRQn<00>DMA2_Stream5_IRQn<00>DMA2_Stream6_IRQn<00>DMA2_Stream7_IRQn<00>USART6_IRQn<00>I2C3_EV_IRQn<00>I2C3_ER_IRQn<00>FPU_IRQn<00>SPI4_IRQn<00>SPI5_IRQn<00>PIRQn_Type<12><01>*<2A> PSR#CR1#CR2#SMPR1# SMPR2#JOFR1#JOFR2#JOFR3#JOFR4# HTR#$LTR#(SQR1#,SQR2#0SQR3#4JSQR#8JDR1#<JDR2#@JDR3#DJDR4#HDR#LtgPADC_TypeDef*<01>*<2A> CSR#CCR#CDR#PADC_Common_TypeDef7<01>*<2A> DR#IDR<12>#RESERVED0H#RESERVED1W#CR#tHPCRC_TypeDefx<01>*<2A>IDCODE#CR#APB1FZ#APB2FZ# PDBGMCU_TypeDef<12><01>*<2A>CR#NDTR#PAR#M0AR# M1AR#FCR#PDMA_Stream_TypeDef,<01>*<2A>LISR#HISR#LIFCR#HIFCR# PDMA_TypeDef<12><01>*<2A>IMR#EMR#RTSR#FTSR# SWIER#PR#PEXTI_TypeDef<12><01>*<2A>ACR#KEYR#OPTKEYR#SR# CR#OPTCR#OPTCR1#PFLASH_TypeDef:<01>*<2A>(MODER#OTYPER#OSPEEDR#PUPDR# IDR#ODR#BSRR#LCKR#<03>AFR # PGPIO_TypeDef<12><01>*<2A>$MEMRMP#PMC#<03>EXTICRZ #<03>gRESERVEDq #CMPCR# PSYSCFG_TypeDef= <01>*<2A>(CR1#CR2#OAR1#OAR2# DR#SR1#SR2#CCR#TRISE# FLTR#$PI2C_TypeDef<12> <01>*<2A>KR#PR#RLR#SR# PIWDG_TypeDef<
<01>*<2A>CR#CSR#PPWR_TypeDef
<01>*<2A><19>CR#PLLCFGR#CFGR#CIR# AHB1RSTR#AHB2RSTR#AHB3RSTR#RESERVED0g#APB1RSTR# APB2RSTR#$<03>gRESERVED1E #(AHB1ENR#0AHB2ENR#4AHB3ENR#8RESERVED2g#<APB1ENR#@APB2ENR#D<03>gRESERVED3<12> #HAHB1LPENR#PAHB2LPENR#TAHB3LPENR#XRESERVED4g#\APB1LPENR#`APB2LPENR#d<03>gRESERVED5C #hBDCR#pCSR#t<03>gRESERVED6v #xSSCGR#<23>PLLI2SCFGR#<23><03>gRESERVED7<12> #<23>DCKCFGR#<23>PRCC_TypeDef<12>
<01>*<2A><1E>TR#DR#CR#ISR# PRER#WUTR#CALIBR#ALRMAR#ALRMBR# WPR#$SSR#(SHIFTR#,TSTR#0TSDR#4TSSSR#8CALR#<TAFCR#@ALRMASSR#DALRMBSSR#HRESERVED7g#LBKP0R#PBKP1R#TBKP2R#XBKP3R#\BKP4R#`BKP5R#dBKP6R#hBKP7R#lBKP8R#pBKP9R#tBKP10R#xBKP11R#|BKP12R#<23>BKP13R#<23>BKP14R#<23>BKP15R#<23>BKP16R#<23>BKP17R#<23>BKP18R#<23>BKP19R#<23>PRTC_TypeDef<12> <01>*<2A> <20>POWER#CLKCR#ARG#CMD# RESPCMDO#RESP1O#RESP2O#RESP3O#RESP4O# DTIMER#$DLEN#(DCTRL#,DCOUNTO#0STAO#4ICR#8MASK#<<03>gRESERVED0<12>#@FIFOCNTO#H<03> g RESERVED1#LFIFO#<23>gtIPSDIO_TypeDef%<01>*<2A>!$CR1#CR2#SR#DR# CRCPR#RXCRCR#TXCRCR#I2SCFGR#I2SPR# PSPI_TypeDefh<01>*<2A>#TCR1#CR2#SMCR#DIER# SR#EGR#CCMR1#CCMR2#CCER# CNT#$PSC#(ARR#,RCR#0CCR1#4CCR2#8CCR3#<CCR4#@BDTR#DDCR#HDMAR#LOR#PPTIM_TypeDef<12><01>*<2A>$SR#DR#BRR#CR1# CR2#CR3#GTPR#PUSART_TypeDef<12><01>*<2A>% CR#CFR#SR#PWWDG_TypeDefb<01>*<2A>'<27>GOTGCTL#GOTGINT#GAHBCFG#GUSBCFG# GRSTCTL#GINTSTS#GINTMSK#GRXSTSR#GRXSTSP# GRXFSIZ#$DIEPTXF0_HNPTXFSIZ#(HNPTXSTS#,<03>&gReserved30`#0GCCFG#8CID#<<03>'g/Reserved40<12>#@HPTXFSIZ#<23><03>'DIEPTXF<12>#<23>PUSB_OTG_GlobalTypeDef<12><01>*<2A>*<2A>DCFG#DCTL#DSTS#Reserved0Cg# DIEPMSK#DOEPMSK#DAINT#DAINTMSK#Reserved20g# Reserved9g#$DVBUSDIS#(DVBUSPULSE#,DTHRCTL#0DIEPEMPMSK#4DEACHINT#8DEACHMSK#<Reserved40g#@DINEP1MSK#D<03>*gReserved44"#HDOUTEP1MSK#<23>PUSB_OTG_DeviceTypeDef<12><01>*<2A>+ DIEPCTL#Reserved04g#DIEPINT#Reserved0Cg# DIEPTSIZ#DIEPDMA#DTXFSTS#Reserved18g#PUSB_OTG_INEndpointTypeDefq<01>*<2A>- DOEPCTL#Reserved04g#DOEPINT#Reserved0Cg# DOEPTSIZ#DOEPDMA#<03>-gReserved18<12>#PUSB_OTG_OUTEndpointTypeDef <01>*<2A>.HCFG#HFIR#HFNUM#Reserved40Cg# HPTXSTS#HAINT#HAINTMSK#PUSB_OTG_HostTypeDef<12><01>*<2A>/ HCCHAR#HCSPLT#HCINT#HCINTMSK# HCTSIZ#HCDMA#<03>/gReserved<12>#PUSB_OTG_HostChannelTypeDefQ<01>qrst__STM32F4xx_HAL_H G__HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))H__HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))I__HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))J__HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))K__HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))L__HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))M__HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))N__HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))O__HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))P__HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))Q__HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))R__HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))S__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))T__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))U__HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>HAL_TICK_FREQ_10HZ dHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ HAL_TICK_FREQ_DEFAULT PHAL_TickFreqTypeDef<12>7tgquwTickfquwTickPriogquwTickFreqK7<00>luwTickyuwTickPrio<00>uwTickFreqvwx&__STM32F4xx_H 4STM32F4 n__STM32F4xx_CMSIS_VERSION_MAIN (0x02U)o__STM32F4xx_CMSIS_VERSION_SUB1 (0x06U)p__STM32F4xx_CMSIS_VERSION_SUB2 (0x0AU)q__STM32F4xx_CMSIS_VERSION_RC (0x00U)r__STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24) |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16) |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F4xx_CMSIS_VERSION_RC))<03><01>IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))<01>SET_BIT(REG,BIT) ((REG) |= (BIT))<01>CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))<01>READ_BIT(REG,BIT) ((REG) & (BIT))<01>CLEAR_REG(REG) ((REG) = (0x0))<01>WRITE_REG(REG,VAL) ((REG) = (VAL))<01>READ_REG(REG) ((REG))<01>MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))<01>POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))<01>ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03><00><00> ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx.hstm32f411xe.hstm32f4xx_hal.h<01>
../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>RESET SET PFlagStatus<12><01>PITStatus<12><01><13>DISABLE ENABLE PFunctionalState(<01><13>SUCCESS ERROR PErrorStatusZ<01>z{|STM32_HAL_LEGACY #AES_FLAG_RDERR CRYP_FLAG_RDERR$AES_FLAG_WRERR CRYP_FLAG_WRERR%AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF&AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR'AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR5ADC_RESOLUTION12b ADC_RESOLUTION_12B6ADC_RESOLUTION10b ADC_RESOLUTION_10B7ADC_RESOLUTION8b ADC_RESOLUTION_8B8ADC_RESOLUTION6b ADC_RESOLUTION_6B9OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN:OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED;EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV<EOC_SEQ_CONV ADC_EOC_SEQ_CONV=EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV>REGULAR_GROUP ADC_REGULAR_GROUP?INJECTED_GROUP ADC_INJECTED_GROUP@REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUPAAWD_EVENT ADC_AWD_EVENTBAWD1_EVENT ADC_AWD1_EVENTCAWD2_EVENT ADC_AWD2_EVENTDAWD3_EVENT ADC_AWD3_EVENTEOVR_EVENT ADC_OVR_EVENTFJQOVF_EVENT ADC_JQOVF_EVENTGALL_CHANNELS ADC_ALL_CHANNELSHREGULAR_CHANNELS ADC_REGULAR_CHANNELSIINJECTED_CHANNELS ADC_INJECTED_CHANNELSJSYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSORKSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINTLADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1MADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2NADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4OADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6PADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8QADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGORADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2SADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGOTADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4UADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGOVADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11WADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1XADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONEYADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISINGZADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING[ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5^HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY_HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY`HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOCaHAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOCbHAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNALcHAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNALdHAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1{__HAL_CEC_GET_IT __HAL_CEC_GET_FLAG<01>COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE<01>COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE<01>COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1<01>COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2<01>COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3<01>COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4<01>COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5<01>COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6<01>COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7<01>COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR<01>__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig<01>HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse<01>HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse<01>CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE<01>CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE<01>DAC1_CHANNEL_1 DAC_CHANNEL_1<01>DAC1_CHANNEL_2 DAC_CHANNEL_2<01>DAC2_CHANNEL_1 DAC_CHANNEL_1<01>DAC_WAVE_NONE 0x00000000U<01>DAC_WAVE_NOISE DAC_CR_WAVE1_0<01>DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1<01>DAC_WAVEGENERATION_NONE DAC_WAVE_NONE<01>DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE<01>DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE<01>HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID<01>HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID<01>HAL_REMAPDMA_ADC_DMA_C
SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE<01>
SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE<01>
SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE<01>
SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE<01>
SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE<01>
SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE<01>
SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE<01>
SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE<01>
SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE<01>
SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE<01>
SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE<01>
SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE<01>
SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE<01>
SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE<01>
SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE<01>
SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE<01>
SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE<01>
SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE<01>
SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE<01>
SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE<01>
HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN<01>
SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE<01>
SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE<01>
SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE<01>
SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE<01>
SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE<01>
SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE<01>
CCER_CCxE_MASK TIM_CCER_CCxE_MASK<01>
CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK<01>
TIM_DMABase_CR1 TIM_DMABASE_CR1<01>
TIM_DMABase_CR2 TIM_DMABASE_CR2<01>
TIM_DMABase_SMCR TIM_DMABASE_SMCR<01>
TIM_DMABase_DIER TIM_DMABASE_DIER<01>
TIM_DMABase_SR TIM_DMABASE_SR<01>
TIM_DMABase_EGR TIM_DMABASE_EGR<01>
TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1<01>
TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2<01>
TIM_DMABase_CCER TIM_DMABASE_CCER<01>
TIM_DMABase_CNT TIM_DMABASE_CNT<01>
TIM_DMABase_PSC TIM_DMABASE_PSC<01>
TIM_DMABase_ARR TIM_DMABASE_ARR<01>
TIM_DMABase_RCR TIM_DMABASE_RCR<01>
TIM_DMABase_CCR1 TIM_DMABASE_CCR1<01>
TIM_DMABase_CCR2 TIM_DMABASE_CCR2<01>
TIM_DMABase_CCR3 TIM_DMABASE_CCR3<01>
TIM_DMABase_CCR4 TIM_DMABASE_CCR4<01>
TIM_DMABase_BDTR TIM_DMABASE_BDTR<01>
TIM_DMABase_DCR TIM_DMABASE_DCR<01>
TIM_DMABase_DMAR TIM_DMABASE_DMAR<01>
TIM_DMABase_OR1 TIM_DMABASE_OR1<01>
TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3<01>
TIM_DMABase_CCR5 TIM_DMABASE_CCR5<01>
TIM_DMABase_CCR6 TIM_DMABASE_CCR6<01>
TIM_DMABase_OR2 TIM_DMABASE_OR2<01>
TIM_DMABase_OR3 TIM_DMABASE_OR3<01>
TIM_DMABase_OR TIM_DMABASE_OR<01>
TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE<01>
TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1<01>
TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2<01>
TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3<01>
TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4<01>
TIM_EventSource_COM TIM_EVENTSOURCE_COM<01>
TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER<01>
TIM_EventSource_Break TIM_EVENTSOURCE_BREAK<01>
TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2<01> TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER<01> TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS<01> TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS<01> TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS<01> TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS<01> TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS<01> TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS<01> TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS<01> TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS<01> TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS<01> TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS<01> TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS<01> TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS<01> TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS<01> TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS<01> TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS<01> TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS<01> TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS<01> TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING<01> TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING<01> UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE<01> UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE<01> UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE<01> UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE<01> __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE<01> __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE<01> __DIV_SAMPLING16 UART_DIV_SAMPLING16<01> __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16<01> __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16<01> __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16<01> __DIV_SAMPLING8 UART_DIV_SAMPLING8<01> __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8<01> __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8<01> __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8<01> __DIV_LPUART UART_DIV_LPUART<01> UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE<01> UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK<01> USART_CLOCK_DISABLED USART_CLOCK_DISABLE<01> USART_CLOCK_ENABLED USART_CLOCK_ENABLE<01> USARTNACK_ENABLED USART_NACK_ENABLE<01> USARTNACK_DISABLED USART_NACK_DISABLE<01> CFR_BASE WWDG_CFR_BASE<01> CAN_FilterFIFO0 CAN_FILTER_FIFO0<01> CAN_FilterFIFO1 CAN_FILTER_FIFO1<01> CAN_IT_RQCP0 CAN_IT_TME<01> CAN_IT_RQCP1 CAN_IT_TME<01> CAN_IT_RQCP2 CAN_IT_TME<01> INAK_TIMEOUT CAN_TIMEOUT_VALUE<01> SLAK_TIMEOUT CAN_TIMEOUT_VALUE<01> CAN_TXSTATUS_FAILED ((uint8_t)0x00U)<01> CAN_TXSTATUS_OK ((uint8_t)0x01U)<01> CAN_TXSTATUS_PENDING ((uint8_t)0x02U)<01> VLAN_TAG ETH_VLAN_TAG<01> MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD<01> MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD<01> JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD<01> MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK<01> MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK<01> MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK<01> DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK<01> ETH_MMCCR 0x00000100U<01> ETH_MMCRIR 0x00000104U<01> ETH_MMCTIR 0x00000108U<01> ETH_MMCRIMR 0x0000010CU<01> ETH_MMCTIMR 0x00000110U<01> ETH_MMCTGFSCCR 0x0000014CU<01> ETH_MMCTGFMSCCR 0x00000150U<01> ETH_MMCTGFCR 0x00000168U<01> ETH_MMCRFCECR 0x00000194U<01> ETH_MMCRFAECR 0x00000198U<01> ETH_MMCRGUFCR 0x000001C4U<01> ETH_MAC_TXFIFO_FULL 0x02000000U<01> ETH_MAC_TXFIFONOT_EMPTY 0x01000000U<01> ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U<01> ETH_MAC_TXFIFO_IDLE 0x00000000U<01> ETH_MAC_TXFIFO_READ 0x00100000U<01> ETH_MAC_TXFIFO_WAITING 0x00200000U<01> ETH_MAC_TXFIFO_WRITING 0x00300000U<01> ETH_MAC_TRANSMISSION_PAUSE 0x00080000U<01> ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U<01> ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U<01> ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U<01> ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U<01> ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U<01> ETH_MAC_RXFIFO_EMPTY 0x00000000U<01> ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U<01> ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U<01> ETH_MAC_RXFIFO_FULL 0x00000300U<01> ETH_MAC_READCONTROLLER_IDLE 0x0000
../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM~<00>__stddef_h __ARMCLIB_VERSION 5060044__STDDEF_DECLS __CLIBNS __CLIBNS SNULLTNULL 0[offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb)))\R E:\Program Files\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hE:\Program Files\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] intunsigned intunsigned shortlong doublePptrdiff_t<12>&Psize_t<12>.Pwchar_t<12>@Pmax_align_t<12>_<00><00><00>__STM32F4xx_HAL_DEF :UNUSED(X) (void)X=HAL_MAX_DELAY 0xFFFFFFFFU?HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) == (BIT))@HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == 0U)B__HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0U)W__HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)]__HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0U)i__HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0U)<01>__ALIGN_END <01>__ALIGN_BEGIN __align(4)<01>__RAM_FUNC <01>__NOINLINE __attribute__ ( (noinline) )<00><00> ../Drivers/STM32F4xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/E:\Program Files\Keil_v5\ARM\ARMCC\Bin\..\include\stm32f4xx_hal_def.hstm32f4xx.hLegacy/stm32_hal_legacy.hstddef.hx
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>HAL_OK HAL_ERROR HAL_BUSY HAL_TIMEOUT PHAL_StatusTypeDef<12>,<13>HAL_UNLOCKED HAL_LOCKED PHAL_LockTypeDef>5<00><00><00>__STM32F4xx_HAL_RCC_EX_H <01>RCC_PERIPHCLK_I2S 0x00000001U<01>RCC_PERIPHCLK_RTC 0x00000002U<01>RCC_PERIPHCLK_PLLI2S 0x00000004U<01>RCC_PERIPHCLK_TIM 0x00000008U<01>RCC_I2SCLKSOURCE_PLLI2S 0x00000000U<01>RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC<01>RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)<01>RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)<01>RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)<01>RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)<01>RCC_MCO2SOURCE_SYSCLK 0x00000000U<01>RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0<01>RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1<01>RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2<01>__HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_GPIOD_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_GPIOE_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_CRC_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))<01>__HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))<01>__HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))<01>__HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))<01>__HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)<01>__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)<01>__HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)<01>__HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)<01>__HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)<01>__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)<01>__HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)<01>__HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)<01>__HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN)); __HAL_RCC_SYSCFG_CLK_ENABLE(); }while(0U)<01>__HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))<01>__HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)<01>__HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)<01>__HAL_RCC_TIM2_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_TIM3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_TIM4_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_SPI3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_I2C3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); UNUSED(tmpreg); } while(0U)<01>__
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>PLLStateg#PLLSourceg#PLLMg#PLLNg# PLLPg#PLLQg#PRCC_PLLInitTypeDef<12>I*<2A> PLLI2SMg#PLLI2SNg#PLLI2SRg#PRCC_PLLI2SInitTypeDefm<01>*<2A>PeriphClockSelectiong#PLLI2S<12>#RTCClockSelectiong#TIMPresSelectionH#PRCC_PeriphCLKInitTypeDef<12><01><00><00><00>__STM32F4xx_HAL_RCC_H jRCC_OSCILLATORTYPE_NONE 0x00000000UkRCC_OSCILLATORTYPE_HSE 0x00000001UlRCC_OSCILLATORTYPE_HSI 0x00000002UmRCC_OSCILLATORTYPE_LSE 0x00000004UnRCC_OSCILLATORTYPE_LSI 0x00000008UvRCC_HSE_OFF 0x00000000UwRCC_HSE_ON RCC_CR_HSEONxRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))<01>RCC_LSE_OFF 0x00000000U<01>RCC_LSE_ON RCC_BDCR_LSEON<01>RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))<01>RCC_HSI_OFF ((uint8_t)0x00)<01>RCC_HSI_ON ((uint8_t)0x01)<01>RCC_HSICALIBRATION_DEFAULT 0x10U<01>RCC_LSI_OFF ((uint8_t)0x00)<01>RCC_LSI_ON ((uint8_t)0x01)<01>RCC_PLL_NONE ((uint8_t)0x00)<01>RCC_PLL_OFF ((uint8_t)0x01)<01>RCC_PLL_ON ((uint8_t)0x02)<01>RCC_PLLP_DIV2 0x00000002U<01>RCC_PLLP_DIV4 0x00000004U<01>RCC_PLLP_DIV6 0x00000006U<01>RCC_PLLP_DIV8 0x00000008U<01>RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI<01>RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE<01>RCC_CLOCKTYPE_SYSCLK 0x00000001U<01>RCC_CLOCKTYPE_HCLK 0x00000002U<01>RCC_CLOCKTYPE_PCLK1 0x00000004U<01>RCC_CLOCKTYPE_PCLK2 0x00000008U<01>RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI<01>RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE<01>RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL<01>RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))<01>RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI<01>RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE<01>RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL<01>RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))<01>RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1<01>RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2<01>RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4<01>RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8<01>RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16<01>RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64<01>RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128<01>RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256<01>RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512<01>RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1<01>RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2<01>RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4<01>RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8<01>RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16<01>RCC_RTCCLKSOURCE_NO_CLK 0x00000000U<01>RCC_RTCCLKSOURCE_LSE 0x00000100U<01>RCC_RTCCLKSOURCE_LSI 0x00000200U<01>RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U<01>RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U<01>RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U<01>RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U<01>RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U<01>RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U<01>RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U<01>RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U<01>RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U<01>RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U<01>RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U<01>RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U<01>RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U<01>RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U<01>RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U<01>RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U<01>RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U<01>RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U<01>RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U<01>RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U<01>RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U<01>RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U<01>RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U<01>RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U<01>RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U<01>RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U<01>RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U<01>RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U<01>RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U<01>RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U<01>RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U<01>RCC_MCO1 0x00000000U<01>RCC_MCO2 0x00000001U<01>RCC_MCO1SOURCE_HSI 0x00000000U
RCC_OFFSET (RCC_BASE - PERIPH_BASE)<01>
RCC_CR_OFFSET (RCC_OFFSET + 0x00U)<01>
RCC_HSION_BIT_NUMBER 0x00U<01>
RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))<01>
RCC_CSSON_BIT_NUMBER 0x13U<01>
RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))<01>
RCC_PLLON_BIT_NUMBER 0x18U<01>
RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))<01>
RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)<01>
RCC_RTCEN_BIT_NUMBER 0x0FU<01>
RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))<01>
RCC_BDRST_BIT_NUMBER 0x10U<01>
RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))<01>
RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)<01>
RCC_LSION_BIT_NUMBER 0x00U<01>
RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))<01>
RCC_CR_BYTE2_ADDRESS 0x40023802U<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))<01>
RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)<01>
RCC_DBP_TIMEOUT_VALUE 2U<01>
RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT<01>
HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT<01>
HSI_TIMEOUT_VALUE 2U<01>
LSI_TIMEOUT_VALUE 2U<01>
CLOCKSWITCH_TIMEOUT_VALUE 5000U<01>
IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)<01>
IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_BYPASS))<01>
IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_BYPASS))<01>
IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))<01>
IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))<01>
IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))<01>
IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || ((SOURCE) == RCC_PLLSOURCE_HSE))<01>
IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))<01> IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))<01> IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))<01> IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))<01> IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))<01> IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))<01> IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || ((PCLK) == RCC_HCLK_DIV16))<01> IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))<01> IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))<01> IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_5))<01> IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)<00><00> ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.hstm32f4xx_hal_def.hstm32f4xx_hal_rcc_ex.h$
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>0OscillatorTypeg#HSEStateg#LSEStateg#HSIStateg# HSICalibrationValueg#LSIStateg#PLLS#PRCC_OscInitTypeDef<12>F*<2A>ClockTypeg#SYSCLKSourceg#AHBCLKDividerg#APB1CLKDividerg# APB2CLKDividerg#PRCC_ClkInitTypeDef<12>\<00><00><00>__STM32F4xx_HAL_GPIO_EX_H <01>GPIO_AF0_RTC_50Hz ((uint8_t)0x00)<01>GPIO_AF0_MCO ((uint8_t)0x00)<01>GPIO_AF0_TAMPER ((uint8_t)0x00)<01>GPIO_AF0_SWJ ((uint8_t)0x00)<01>GPIO_AF0_TRACE ((uint8_t)0x00)<01>GPIO_AF1_TIM1 ((uint8_t)0x01)<01>GPIO_AF1_TIM2 ((uint8_t)0x01)<01>GPIO_AF2_TIM3 ((uint8_t)0x02)<01>GPIO_AF2_TIM4 ((uint8_t)0x02)<01>GPIO_AF2_TIM5 ((uint8_t)0x02)<01>GPIO_AF3_TIM9 ((uint8_t)0x03)<01>GPIO_AF3_TIM10 ((uint8_t)0x03)<01>GPIO_AF3_TIM11 ((uint8_t)0x03)<01>GPIO_AF4_I2C1 ((uint8_t)0x04)<01>GPIO_AF4_I2C2 ((uint8_t)0x04)<01>GPIO_AF4_I2C3 ((uint8_t)0x04)<01>GPIO_AF5_SPI1 ((uint8_t)0x05)<01>GPIO_AF5_SPI2 ((uint8_t)0x05)<01>GPIO_AF5_SPI3 ((uint8_t)0x05)<01>GPIO_AF5_SPI4 ((uint8_t)0x05)<01>GPIO_AF5_I2S3ext ((uint8_t)0x05)<01>GPIO_AF6_SPI2 ((uint8_t)0x06)<01>GPIO_AF6_SPI3 ((uint8_t)0x06)<01>GPIO_AF6_SPI4 ((uint8_t)0x06)<01>GPIO_AF6_SPI5 ((uint8_t)0x06)<01>GPIO_AF6_I2S2ext ((uint8_t)0x06)<01>GPIO_AF7_SPI3 ((uint8_t)0x07)<01>GPIO_AF7_USART1 ((uint8_t)0x07)<01>GPIO_AF7_USART2 ((uint8_t)0x07)<01>GPIO_AF7_I2S3ext ((uint8_t)0x07)<01>GPIO_AF8_USART6 ((uint8_t)0x08)<01>GPIO_AF9_TIM14 ((uint8_t)0x09)<01>GPIO_AF9_I2C2 ((uint8_t)0x09)<01>GPIO_AF9_I2C3 ((uint8_t)0x09)<01>GPIO_AF10_OTG_FS ((uint8_t)0x0A)<01>GPIO_AF12_SDIO ((uint8_t)0x0C)<01>GPIO_AF15_EVENTOUT ((uint8_t)0x0F)<01>
GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U : ((__GPIOx__) == (GPIOB))? 1U : ((__GPIOx__) == (GPIOC))? 2U : ((__GPIOx__) == (GPIOD))? 3U : ((__GPIOx__) == (GPIOE))? 4U : 7U)<01> IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))tj ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.hstm32f4xx_hal_def.h<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<00><00><00>__STM32F4xx_HAL_GPIO_H UGPIO_PIN_0 ((uint16_t)0x0001)VGPIO_PIN_1 ((uint16_t)0x0002)WGPIO_PIN_2 ((uint16_t)0x0004)XGPIO_PIN_3 ((uint16_t)0x0008)YGPIO_PIN_4 ((uint16_t)0x0010)ZGPIO_PIN_5 ((uint16_t)0x0020)[GPIO_PIN_6 ((uint16_t)0x0040)\GPIO_PIN_7 ((uint16_t)0x0080)]GPIO_PIN_8 ((uint16_t)0x0100)^GPIO_PIN_9 ((uint16_t)0x0200)_GPIO_PIN_10 ((uint16_t)0x0400)`GPIO_PIN_11 ((uint16_t)0x0800)aGPIO_PIN_12 ((uint16_t)0x1000)bGPIO_PIN_13 ((uint16_t)0x2000)cGPIO_PIN_14 ((uint16_t)0x4000)dGPIO_PIN_15 ((uint16_t)0x8000)eGPIO_PIN_All ((uint16_t)0xFFFF)gGPIO_PIN_MASK 0x0000FFFFUuGPIO_MODE_INPUT MODE_INPUTvGPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)wGPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)xGPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)yGPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD){GPIO_MODE_ANALOG MODE_ANALOG}GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)~GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)<01>GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)<01>GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)<01>GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)<01>GPIO_SPEED_FREQ_LOW 0x00000000U<01>GPIO_SPEED_FREQ_MEDIUM 0x00000001U<01>GPIO_SPEED_FREQ_HIGH 0x00000002U<01>GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U<01>GPIO_NOPULL 0x00000000U<01>GPIO_PULLUP 0x00000001U<01>GPIO_PULLDOWN 0x00000002U<01>__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))<03><01>GPIO_MODE_Pos 0U<01>GPIO_MODE (0x3UL << GPIO_MODE_Pos)<01>MODE_INPUT (0x0UL << GPIO_MODE_Pos)<01>MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)<01>MODE_AF (0x2UL << GPIO_MODE_Pos)<01>MODE_ANALOG (0x3UL << GPIO_MODE_Pos)<01>OUTPUT_TYPE_Pos 4U<01>OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)<01>OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)<01>OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)<01>EXTI_MODE_Pos 16U<01>EXTI_MODE (0x3UL << EXTI_MODE_Pos)<01>EXTI_IT (0x1UL << EXTI_MODE_Pos)<01>EXTI_EVT (0x2UL << EXTI_MODE_Pos)<01>TRIGGER_MODE_Pos 20U<01>TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)<01>TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)<01>TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)<01>IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))<01>IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))<01>IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || ((MODE) == GPIO_MODE_ANALOG))<01>IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))<01>IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))<00><00> ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.hstm32f4xx_hal_def.hstm32f4xx_hal_gpio_ex.h<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>Ping#Modeg#Pullg#Speedg# Alternateg#PGPIO_InitTypeDef<12>><13>GPIO_PIN_RESET GPIO_PIN_SET PGPIO_PinStateWG<00><00><00>STM32f4xx_HAL_EXTI_H VEXTI_LINE_0 (EXTI_GPIO | 0x00u)WEXTI_LINE_1 (EXTI_GPIO | 0x01u)XEXTI_LINE_2 (EXTI_GPIO | 0x02u)YEXTI_LINE_3 (EXTI_GPIO | 0x03u)ZEXTI_LINE_4 (EXTI_GPIO | 0x04u)[EXTI_LINE_5 (EXTI_GPIO | 0x05u)\EXTI_LINE_6 (EXTI_GPIO | 0x06u)]EXTI_LINE_7 (EXTI_GPIO | 0x07u)^EXTI_LINE_8 (EXTI_GPIO | 0x08u)_EXTI_LINE_9 (EXTI_GPIO | 0x09u)`EXTI_LINE_10 (EXTI_GPIO | 0x0Au)aEXTI_LINE_11 (EXTI_GPIO | 0x0Bu)bEXTI_LINE_12 (EXTI_GPIO | 0x0Cu)cEXTI_LINE_13 (EXTI_GPIO | 0x0Du)dEXTI_LINE_14 (EXTI_GPIO | 0x0Eu)eEXTI_LINE_15 (EXTI_GPIO | 0x0Fu)fEXTI_LINE_16 (EXTI_CONFIG | 0x10u)gEXTI_LINE_17 (EXTI_CONFIG | 0x11u)iEXTI_LINE_18 (EXTI_CONFIG | 0x12u)nEXTI_LINE_19 (EXTI_CONFIG | 0x13u)sEXTI_LINE_20 (EXTI_CONFIG | 0x14u)wEXTI_LINE_21 (EXTI_CONFIG | 0x15u)xEXTI_LINE_22 (EXTI_CONFIG | 0x16u)<01>EXTI_MODE_NONE 0x00000000u<01>EXTI_MODE_INTERRUPT 0x00000001u<01>EXTI_MODE_EVENT 0x00000002u<01>EXTI_TRIGGER_NONE 0x00000000u<01>EXTI_TRIGGER_RISING 0x00000001u<01>EXTI_TRIGGER_FALLING 0x00000002u<01>EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)<01>EXTI_GPIOA 0x00000000u<01>EXTI_GPIOB 0x00000001u<01>EXTI_GPIOC 0x00000002u<01>EXTI_GPIOD 0x00000003u<01>EXTI_GPIOE 0x00000004u<01>EXTI_GPIOH 0x00000007u<01>EXTI_PROPERTY_SHIFT 24u<01>EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)<01>EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)<01>EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)<01>EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)<01>EXTI_PIN_MASK 0x0000001Fu<01>EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)<01>EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)<01>EXTI_LINE_NB 23UL<01>IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))<01>IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))<01>IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)<01>IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)<01>IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)<01>IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOH))<01>IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)pg ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.hstm32f4xx_hal_def.h<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>HAL_EXTI_COMMON_CB_ID PEXTI_CallbackIDTypeDef<12>/*<2A>Lineg#O<>"=PendingCallbackA#PEXTI_HandleTypeDef+8*<2A>Lineg#Modeg#Triggerg#GPIOSelg# PEXTI_ConfigTypeDefwH<00><00><00>__STM32F4xx_HAL_DMA_EX_H ti ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.hstm32f4xx_hal_def.h(
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>MEMORY0 MEMORY1 PHAL_DMA_MemoryTypeDef<12>3<00><00><00>__STM32F4xx_HAL_DMA_H <01>HAL_DMA_ERROR_NONE 0x00000000U<01>HAL_DMA_ERROR_TE 0x00000001U<01>HAL_DMA_ERROR_FE 0x00000002U<01>HAL_DMA_ERROR_DME 0x00000004U<01>HAL_DMA_ERROR_TIMEOUT 0x00000020U<01>HAL_DMA_ERROR_PARAM 0x00000040U<01>HAL_DMA_ERROR_NO_XFER 0x00000080U<01>HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U<01>DMA_CHANNEL_0 0x00000000U<01>DMA_CHANNEL_1 0x02000000U<01>DMA_CHANNEL_2 0x04000000U<01>DMA_CHANNEL_3 0x06000000U<01>DMA_CHANNEL_4 0x08000000U<01>DMA_CHANNEL_5 0x0A000000U<01>DMA_CHANNEL_6 0x0C000000U<01>DMA_CHANNEL_7 0x0E000000U<01>DMA_PERIPH_TO_MEMORY 0x00000000U<01>DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)<01>DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)<01>DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)<01>DMA_PINC_DISABLE 0x00000000U<01>DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)<01>DMA_MINC_DISABLE 0x00000000U<01>DMA_PDATAALIGN_BYTE 0x00000000U<01>DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)<01>DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)<01>DMA_MDATAALIGN_BYTE 0x00000000U<01>DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)<01>DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)<01>DMA_NORMAL 0x00000000U<01>DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)<01>DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)<01>DMA_PRIORITY_LOW 0x00000000U<01>DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)<01>DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)<01>DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)<01>DMA_FIFOMODE_DISABLE 0x00000000U<01>DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)<01>DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U<01>DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)<01>DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)<01>DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)<01>DMA_MBURST_SINGLE 0x00000000U<01>DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)<01>DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)<01>DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)<01>DMA_PBURST_SINGLE 0x00000000U<01>DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)<01>DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)<01>DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)<01>DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)<01>DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)<01>DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)<01>DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)<01>DMA_IT_FE 0x00000080U<01>DMA_FLAG_FEIF0_4 0x00000001U<01>DMA_FLAG_DMEIF0_4 0x00000004U<01>DMA_FLAG_TEIF0_4 0x00000008U<01>DMA_FLAG_HTIF0_4 0x00000010U<01>DMA_FLAG_TCIF0_4 0x00000020U<01>DMA_FLAG_FEIF1_5 0x00000040U<01>DMA_FLAG_DMEIF1_5 0x00000100U<01>DMA_FLAG_TEIF1_5 0x00000200U<01>DMA_FLAG_HTIF1_5 0x00000400U<01>DMA_FLAG_TCIF1_5 0x00000800U<01>DMA_FLAG_FEIF2_6 0x00010000U<01>DMA_FLAG_DMEIF2_6 0x00040000U<01>DMA_FLAG_TEIF2_6 0x00080000U<01>DMA_FLAG_HTIF2_6 0x00100000U<01>DMA_FLAG_TCIF2_6 0x00200000U<01>DMA_FLAG_FEIF3_7 0x00400000U<01>DMA_FLAG_DMEIF3_7 0x01000000U<01>DMA_FLAG_TEIF3_7 0x02000000U<01>DMA_FLAG_HTIF3_7 0x04000000U<01>DMA_FLAG_TCIF3_7 0x08000000U<01>__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)<01>__HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))<01>__HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)<01>__HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)<01>__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 : ((uint
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARMuvoid"<12>"tgPDMA_InitTypeDef<12>`PHAL_DMA_StateTypeDef<12>nPHAL_DMA_LevelCompleteTypeDefwPHAL_DMA_CallbackIDTypeDefO<01>PDMA_HandleTypeDef<01>*<2A>0Channelg#Directiong#PeriphIncg#MemIncg# PeriphDataAlignmentg#MemDataAlignmentg#Modeg#Priorityg#FIFOModeg# FIFOThresholdg#$MemBurstg#(PeriphBurstg#,<13>HAL_DMA_STATE_RESET HAL_DMA_STATE_READY HAL_DMA_STATE_BUSY HAL_DMA_STATE_TIMEOUT HAL_DMA_STATE_ERROR HAL_DMA_STATE_ABORT <13>HAL_DMA_FULL_TRANSFER HAL_DMA_HALF_TRANSFER <13>HAL_DMA_XFER_CPLT_CB_ID HAL_DMA_XFER_HALFCPLT_CB_ID HAL_DMA_XFER_M1CPLT_CB_ID HAL_DMA_XFER_M1HALFCPLT_CB_ID HAL_DMA_XFER_ERROR_CB_ID HAL_DMA_XFER_ABORT_CB_ID HAL_DMA_XFER_ALL_CB_ID )<29> __DMA_HandleTypeDef`Instance<12>#Init#Locka#4State<12>#5Parent<12>#8O<38> %<12>"{XferCpltCallback<12>#<O<> %<12>"<12>XferHalfCpltCallback<12>#@O<> %<12>"<12>XferM1CpltCallback<12>#DO<44> %<12>"<12>XferM1HalfCpltCallback<12>#HO<48>
%<12>"XferErrorCallback#LO<4C>
%<12>"<XferAbortCallbackD#PErrorCode<12>#TStreamBaseAddressg#XStreamIndexg#\"ut<00><00><00>__STM32F4xx_HAL_CORTEX_H XNVIC_PRIORITYGROUP_0 0x00000007UZNVIC_PRIORITYGROUP_1 0x00000006U\NVIC_PRIORITYGROUP_2 0x00000005U^NVIC_PRIORITYGROUP_3 0x00000004U`NVIC_PRIORITYGROUP_4 0x00000003UiSYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UjSYSTICK_CLKSOURCE_HCLK 0x00000004UtMPU_HFNMI_PRIVDEF_NONE 0x00000000UuMPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_MskvMPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_MskwMPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)<01>MPU_REGION_ENABLE ((uint8_t)0x01)<01>MPU_REGION_DISABLE ((uint8_t)0x00)<01>MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)<01>MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)<01>MPU_ACCESS_SHAREABLE ((uint8_t)0x01)<01>MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)<01>MPU_ACCESS_CACHEABLE ((uint8_t)0x01)<01>MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)<01>MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)<01>MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)<01>MPU_TEX_LEVEL0 ((uint8_t)0x00)<01>MPU_TEX_LEVEL1 ((uint8_t)0x01)<01>MPU_TEX_LEVEL2 ((uint8_t)0x02)<01>MPU_REGION_SIZE_32B ((uint8_t)0x04)<01>MPU_REGION_SIZE_64B ((uint8_t)0x05)<01>MPU_REGION_SIZE_128B ((uint8_t)0x06)<01>MPU_REGION_SIZE_256B ((uint8_t)0x07)<01>MPU_REGION_SIZE_512B ((uint8_t)0x08)<01>MPU_REGION_SIZE_1KB ((uint8_t)0x09)<01>MPU_REGION_SIZE_2KB ((uint8_t)0x0A)<01>MPU_REGION_SIZE_4KB ((uint8_t)0x0B)<01>MPU_REGION_SIZE_8KB ((uint8_t)0x0C)<01>MPU_REGION_SIZE_16KB ((uint8_t)0x0D)<01>MPU_REGION_SIZE_32KB ((uint8_t)0x0E)<01>MPU_REGION_SIZE_64KB ((uint8_t)0x0F)<01>MPU_REGION_SIZE_128KB ((uint8_t)0x10)<01>MPU_REGION_SIZE_256KB ((uint8_t)0x11)<01>MPU_REGION_SIZE_512KB ((uint8_t)0x12)<01>MPU_REGION_SIZE_1MB ((uint8_t)0x13)<01>MPU_REGION_SIZE_2MB ((uint8_t)0x14)<01>MPU_REGION_SIZE_4MB ((uint8_t)0x15)<01>MPU_REGION_SIZE_8MB ((uint8_t)0x16)<01>MPU_REGION_SIZE_16MB ((uint8_t)0x17)<01>MPU_REGION_SIZE_32MB ((uint8_t)0x18)<01>MPU_REGION_SIZE_64MB ((uint8_t)0x19)<01>MPU_REGION_SIZE_128MB ((uint8_t)0x1A)<01>MPU_REGION_SIZE_256MB ((uint8_t)0x1B)<01>MPU_REGION_SIZE_512MB ((uint8_t)0x1C)<01>MPU_REGION_SIZE_1GB ((uint8_t)0x1D)<01>MPU_REGION_SIZE_2GB ((uint8_t)0x1E)<01>MPU_REGION_SIZE_4GB ((uint8_t)0x1F)<01>MPU_REGION_NO_ACCESS ((uint8_t)0x00)<01>MPU_REGION_PRIV_RW ((uint8_t)0x01)<01>MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)<01>MPU_REGION_FULL_ACCESS ((uint8_t)0x03)<01>MPU_REGION_PRIV_RO ((uint8_t)0x05)<01>MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)<01>MPU_REGION_NUMBER0 ((uint8_t)0x00)<01>MPU_REGION_NUMBER1 ((uint8_t)0x01)<01>MPU_REGION_NUMBER2 ((uint8_t)0x02)<01>MPU_REGION_NUMBER3 ((uint8_t)0x03)<01>MPU_REGION_NUMBER4 ((uint8_t)0x04)<01>MPU_REGION_NUMBER5 ((uint8_t)0x05)<01>MPU_REGION_NUMBER6 ((uint8_t)0x06)<01>MPU_REGION_NUMBER7 ((uint8_t)0x07)<01>IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))<01>IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)<01>IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)<01>IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)<01>IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))<01>IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))<01>IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))<01>IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))<01>IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))<01>IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))<01>IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))<01>IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRI
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>EnableH#NumberH#BaseAddressg#SizeH#SubRegionDisableH# TypeExtFieldH#
AccessPermissionH# DisableExecH# IsShareableH# IsCacheableH#IsBufferableH#PMPU_Region_InitTypeDef<12>E<00><00><00>__STM32F4xx_LL_ADC_H 7ADC_SQR1_REGOFFSET 0x00000000UL8ADC_SQR2_REGOFFSET 0x00000100UL9ADC_SQR3_REGOFFSET 0x00000200UL:ADC_SQR4_REGOFFSET 0x00000300UL<ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)=ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)AADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL)BADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL)CADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL)DADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL)EADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL)FADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL)GADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL)HADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL)IADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL)JADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL)KADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL)LADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL)MADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL)NADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL)OADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL)PADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL)ZADC_JDR1_REGOFFSET 0x00000000UL[ADC_JDR2_REGOFFSET 0x00000100UL\ADC_JDR3_REGOFFSET 0x00000200UL]ADC_JDR4_REGOFFSET 0x00000300ULaADC_JOFR1_REGOFFSET 0x00000000ULbADC_JOFR2_REGOFFSET 0x00001000ULcADC_JOFR3_REGOFFSET 0x00002000ULdADC_JOFR4_REGOFFSET 0x00003000ULfADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)gADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)hADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)nADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0)sADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | ((ADC_CR2_EXTSEL) >> (4UL * 3UL))){ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))<01>ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL)<01>ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL)<01>ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0)<01>ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | ((ADC_CR2_JEXTSEL) >> (4UL * 3UL)))<01>ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))<01>ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL)<01>ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL)<01>ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)<01>ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)<01>ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)<01>ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU<01>ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL<01>ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL<01>ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U<01>ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)<01>ADC_SMPR1_REGOFFSET 0x00000000UL<01>ADC_SMPR2_REGOFFSET 0x02000000UL<01>ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)<01>ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL<01>ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL)<01>ADC_CHANNEL_0_NUMBER 0x00000000UL<01>ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)<01>ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )<01>ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)<01>ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )<01>ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)<01>ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )<01>ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)<01>
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__,__CHANNEL__) ( ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) )<01> __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__,__GROUP__) (((__GROUP__) == LL_ADC_GROUP_REGULAR) ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) : ((__GROUP__) == LL_ADC_GROUP_INJECTED) ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) : (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) )<01> __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__,__AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))<01> __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__,__AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))<01> __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)<01> __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1))<01> __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))<01> __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,__ADC_RESOLUTION_CURRENT__,__ADC_RESOLUTION_TARGET__) (((__DATA__) << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) )<01> __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,__ADC_DATA__,__ADC_RESOLUTION__) ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) )<01> __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,__ADC_RESOLUTION__) (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), (__ADC_RESOLUTION__), LL_ADC_RESOLUTION_12B))<01> __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,__TEMPSENSOR_ADC_DATA__,__ADC_RESOLUTION__) (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), (__ADC_RESOLUTION__), LL_ADC_RESOLUTION_12B) * (__VREFANALOG_VOLTAGE__)) / TEMPSENSOR_CAL_VREFANALOG) - (int32_t) *TEMPSENSOR_CAL1_ADDR) ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) ) + TEMPSENSOR_CAL1_TEMP )<01>__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,__TEMPSENSOR_TYP_CALX_V__,__TEMPSENSOR_CALX_TEMP__,__VREFANALOG_VOLTAGE__,__TEMPSENSOR_ADC_DATA__,__ADC_RESOLUTION__) ((( ( (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) * 1000) - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) * 1000) ) ) / (__TEMPSENSOR_TYP_AVGSLOPE__) ) + (__TEMPSENSOR_CALX_TEMP__) )<00><00> ../Drivers/STM32F4xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx_ll_adc.hstm32f4xx.h<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM;<3B><01>LL_ADC_DMA_GetRegAddrg$9ADCx$gRegistera__resultg"#<<3C><01>LL_ADC_SetCommonClock$<12>ADCxy_COMMON$gCommonClock"];<3B><01>LL_ADC_GetCommonClockg$<12>ADCxy_COMMONa__resultg]"<12><<3C><01>LL_ADC_SetCommonPathInternalCh$<12>ADCxy_COMMON$gPathInternal;<3B><01>LL_ADC_GetCommonPathInternalChg$<12>ADCxy_COMMONa__resultg<<3C><01>LL_ADC_SetResolution$9ADCx$gResolution;<3B><01>LL_ADC_GetResolutiong$<12>ADCxa__resultg#"<12><<3C><01>LL_ADC_SetDataAlignment$9ADCx$gDataAlignment;<3B><01>LL_ADC_GetDataAlignmentg$<12>ADCxa__resultg<<3C><01>LL_ADC_SetSequencersScanMode$9ADCx$gScanMode;<3B><01>LL_ADC_GetSequencersScanModeg$<12>ADCxa__resultg<<3C><01>LL_ADC_REG_SetTriggerSource$9ADCx$gTriggerSource;<3B> <01>LL_ADC_REG_GetTriggerSourceg$<12>ADCxa__resultg\TriggerSourceg\ShiftExteng;<3B> <01>LL_ADC_REG_IsTriggerSourceSWStartg$<12>ADCxa__resultg;<3B>
<01>LL_ADC_REG_GetTriggerEdgeg$<12>ADCxa__resultg<<3C>
<01>LL_ADC_REG_SetSequencerLength$9ADCx$gSequencerNbRanks;<3B> <01>LL_ADC_REG_GetSequencerLengthg$<12>ADCxa__resultg<<3C> <01>LL_ADC_REG_SetSequencerDiscont$9ADCx$gSeqDiscont;<3B> <01>LL_ADC_REG_GetSequencerDiscontg$<12>ADCxa__resultg<<3C> <01>LL_ADC_REG_SetSequencerRanks$9ADCx$gRank$gChannel\preg<12>tg"<12>;<3B> <01>LL_ADC_REG_GetSequencerRanksg$<12>ADCx$gRanka__resultg\preg<12>gt<12>"<12><<3C><01>LL_ADC_REG_SetContinuousMode$9ADCx$gContinuous;<3B><01>LL_ADC_REG_GetContinuousModeg$<12>ADCxa__resultg<<3C><01>LL_ADC_REG_SetDMATransfer$9ADCx$gDMATransfer;<3B><01>LL_ADC_REG_GetDMATransferg$<12>ADCxa__resultg<<3C><01>LL_ADC_REG_SetFlagEndOfConversion$9ADCx$gEocSelection;<3B><01>LL_ADC_REG_GetFlagEndOfConversiong$<12>ADCxa__resultg<<3C><01>LL_ADC_INJ_SetTriggerSource$9ADCx$gTriggerSource;<3B><01>LL_ADC_INJ_GetTriggerSourceg$<12>ADCxa__resultg\TriggerSourceg\ShiftExteng;<3B><01>LL_ADC_INJ_IsTriggerSourceSWStartg$<12>ADCxa__resultg;<3B><01>LL_ADC_INJ_GetTriggerEdgeg$<12>ADCxa__resultg<<3C><01>LL_ADC_INJ_SetSequencerLength$9ADCx$gSequencerNbRanks;<3B><01>LL_ADC_INJ_GetSequencerLengthg$<12>ADCxa__resultg<<3C><01>LL_ADC_INJ_SetSequencerDiscont$9ADCx$gSeqDiscont;<3B><01>LL_ADC_INJ_GetSequencerDiscontg$<12>ADCxa__resultg<<3C><01>LL_ADC_INJ_SetSequencerRanks$9ADCx$gRank$gChannel\tmpreg1g;<3B><01>LL_ADC_INJ_GetSequencerRanksg$<12>ADCx$gRanka__resultg\tmpreg1g<<3C><01>LL_ADC_INJ_SetTrigAuto$9ADCx$gTrigAuto;<3B><01>LL_ADC_INJ_GetTrigAutog$<12>ADCxa__resultg<<3C><01>LL_ADC_INJ_SetOffset$9ADCx$gRank$gOffsetLevel\preg<12>;<3B><01>LL_ADC_INJ_GetOffsetg$<12>ADCx$gRanka__resultg\preg<12><<3C><01>LL_ADC_SetChannelSamplingTime$9ADCx$gChannel$gSamplingTime\preg<12>;<3B><01>LL_ADC_GetChannelSamplingTimeg$<12>ADCx$gChannela__resultg\preg<12><<3C><01>LL_ADC_SetAnalogWDMonitChannels$9ADCx$gAWDChannelGroup;<3B><01>LL_ADC_GetAnalogWDMonitChannelsg$<12>ADCxa__resultg<<3C><01>LL_ADC_SetAnalogWDThresholds$9ADCx$gAWDThresholdsHighLow$gAWDThresholdValue\preg<12>;<3B><01>LL_ADC_GetAnalogWDThresholdsg$<12>ADCx$gAWDThresholdsHighLowa__resultg\preg<12><<3C><01>LL_ADC_Enable$9ADCx<<3C><01>LL_ADC_Disable$9ADCx;<3B><01>LL_ADC_IsEnabledg$<12>ADCxa__resultg<<3C><01>LL_ADC_REG_StartConversionSWStart$9ADCx<<3C><01>LL_ADC_REG_StartConversionExtTrig$9ADCx$gExternalTriggerEdge<<3C><01>LL_ADC_REG_StopConversionExtTrig$9ADCx;<3B> <01>LL_ADC_REG_ReadConversionData32g$<12>ADCxa__resultg;<3B> <01>LL_ADC_REG_ReadConversionData12W$<12>ADCxa__resultW;<3B>!<01>LL_ADC_REG_ReadConversionData10W$<12>ADCxa__resultW;<3B>!<01>LL_ADC_REG_ReadConversionData8H$<12>ADCxa__resultH;<3B>"<01>LL_ADC_REG_ReadConversionData6H$<12>ADCxa__resultH<<3C>"<01>LL_ADC_INJ_StartConversionSWStart$9ADCx<<3C>#<01> LL_ADC_INJ_StartConversionExtTrig$9ADCx$gExternalTriggerEdge<<3C>#<01> LL_ADC_INJ_StopConversionExtTrig$9ADCx;<3B>$<01> LL_ADC_INJ_ReadConversionData32g$<12>ADCx$gRanka__resultg\preg<12>;<3B>%<01> LL_ADC_INJ_ReadConversionData12W$<12>ADCx$gRanka__resultW\preg<12>;<3B>&<01> LL_ADC_INJ_ReadConversionData10W$<12>ADCx$gRanka__resultW\preg<12>;<3B>&<01>!LL_ADC_INJ_ReadConversionData8H$<12>ADCx$gRanka__resultH\preg<12>;<3B>'<01>!LL_ADC_INJ_ReadConversionData6H$<12>ADCx$gRanka__resultH\preg<12>;<3B>'<01>!LL_ADC_IsActiveFlag_EOCSg$<12>ADCxa__resultg;<3B>(<01>!LL_ADC_IsActiveFlag_OVRg$<12>ADCxa__resultg;<3B>(<01>!LL_ADC_IsActiveFlag_JEOSg$<12>ADCxa__resultg;<3B>)<01>!LL_ADC_IsActiveFlag_AWD1g$<12>ADCxa__resultg<<3C>)<01>!LL_ADC_ClearFlag_EOCS$9ADCx<<3C>*<01>"LL_ADC_ClearFlag_OVR$9ADCx<<3C>*<01>"LL_ADC_ClearFlag_JEOS
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A> InjectedChannelg#InjectedRankg#InjectedSamplingTimeg#InjectedOffsetg# InjectedNbrOfConversiong#InjectedDiscontinuousConvModeB#AutoInjectedConvB#ExternalTrigInjecConvg#ExternalTrigInjecConvEdgeg#PADC_InjectionConfTypeDef<12>m*<2A> Modeg#DMAAccessModeg#TwoSamplingDelayg#PADC_MultiModeTypeDefz<00><00><00>__STM32F4xx_ADC_H <01>HAL_ADC_STATE_RESET 0x00000000U<01>HAL_ADC_STATE_READY 0x00000001U<01>HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U<01>HAL_ADC_STATE_TIMEOUT 0x00000004U<01>HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U<01>HAL_ADC_STATE_ERROR_CONFIG 0x00000020U<01>HAL_ADC_STATE_ERROR_DMA 0x00000040U<01>HAL_ADC_STATE_REG_BUSY 0x00000100U<01>HAL_ADC_STATE_REG_EOC 0x00000200U<01>HAL_ADC_STATE_REG_OVR 0x00000400U<01>HAL_ADC_STATE_INJ_BUSY 0x00001000U<01>HAL_ADC_STATE_INJ_EOC 0x00002000U<01>HAL_ADC_STATE_AWD1 0x00010000U<01>HAL_ADC_STATE_AWD2 0x00020000U<01>HAL_ADC_STATE_AWD3 0x00040000U<01>HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U<01>HAL_ADC_ERROR_NONE 0x00U<01>HAL_ADC_ERROR_INTERNAL 0x01U<01>HAL_ADC_ERROR_OVR 0x02U<01>HAL_ADC_ERROR_DMA 0x04U<01>ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U<01>ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)<01>ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)<01>ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)<01>ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U<01>ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)<01>ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)<01>ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))<01>ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)<01>ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))<01>ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))<01>ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))<01>ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)<01>ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))<01>ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))<01>ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))<01>ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))<01>ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))<01>ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))<01>ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)<01>ADC_RESOLUTION_12B 0x00000000U<01>ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)<01>ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)<01>ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)<01>ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U<01>ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)<01>ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)<01>ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)<01>ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U<01>ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)<01>ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)<01>ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))<01>ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)<01>ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))<01>ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))<01>ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))<01>ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)<01>ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))<01>ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))<01>ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXT
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>0ClockPrescalerg#Resolutiong#DataAligng#ScanConvModeg# EOCSelectiong#ContinuousConvModeB#NbrOfConversiong#DiscontinuousConvModeB#NbrOfDiscConversiong# ExternalTrigConvg#$ExternalTrigConvEdgeg#(DMAContinuousRequestsB#,PADC_InitTypeDef<12>l*<2A>Channelg#Rankg#SamplingTimeg#Offsetg# PADC_ChannelConfTypeDef=<01>*<2A>WatchdogModeg#HighThresholdg#LowThresholdg#Channelg# ITModeB#WatchdogNumberg#PADC_AnalogWDGConfTypeDef<12><01>*<2A>HInstance<12>#Init&#NbrOfCurrentConversionRank<12>#4DMA_Handle<12>#8Locka#<State<12>#@ErrorCode<12>#D"#tg"{PADC_HandleTypeDefH<01><00><00><00>__STM32F4xx_HAL_FLASH_EX_H <01>FLASH_TYPEERASE_SECTORS 0x00000000U<01>FLASH_TYPEERASE_MASSERASE 0x00000001U<01>FLASH_VOLTAGE_RANGE_1 0x00000000U<01>FLASH_VOLTAGE_RANGE_2 0x00000001U<01>FLASH_VOLTAGE_RANGE_3 0x00000002U<01>FLASH_VOLTAGE_RANGE_4 0x00000003U<01>OB_WRPSTATE_DISABLE 0x00000000U<01>OB_WRPSTATE_ENABLE 0x00000001U<01>OPTIONBYTE_WRP 0x00000001U<01>OPTIONBYTE_RDP 0x00000002U<01>OPTIONBYTE_USER 0x00000004U<01>OPTIONBYTE_BOR 0x00000008U<01>OB_RDP_LEVEL_0 ((uint8_t)0xAA)<01>OB_RDP_LEVEL_1 ((uint8_t)0x55)<01>OB_RDP_LEVEL_2 ((uint8_t)0xCC)<01>OB_IWDG_SW ((uint8_t)0x20)<01>OB_IWDG_HW ((uint8_t)0x00)<01>OB_STOP_NO_RST ((uint8_t)0x40)<01>OB_STOP_RST ((uint8_t)0x00)<01>OB_STDBY_NO_RST ((uint8_t)0x80)<01>OB_STDBY_RST ((uint8_t)0x00)<01>OB_BOR_LEVEL3 ((uint8_t)0x00)<01>OB_BOR_LEVEL2 ((uint8_t)0x04)<01>OB_BOR_LEVEL1 ((uint8_t)0x08)<01>OB_BOR_OFF ((uint8_t)0x0C)<01>OB_PCROP_STATE_DISABLE 0x00000000U<01>OB_PCROP_STATE_ENABLE 0x00000001U<01>OPTIONBYTE_PCROP 0x00000001U<01>FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS<01>FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS<01>FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS<01>FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS<01>FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS<01>FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS<01>FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS<01>FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS<01>FLASH_BANK_1 1U<01>FLASH_MER_BIT (FLASH_CR_MER)<01>FLASH_SECTOR_0 0U<01>FLASH_SECTOR_1 1U<01>FLASH_SECTOR_2 2U<01>FLASH_SECTOR_3 3U<01>FLASH_SECTOR_4 4U<01>FLASH_SECTOR_5 5U<01>FLASH_SECTOR_6 6U<01>FLASH_SECTOR_7 7U<01>OB_WRP_SECTOR_0 0x00000001U<01>OB_WRP_SECTOR_1 0x00000002U<01>OB_WRP_SECTOR_2 0x00000004U<01>OB_WRP_SECTOR_3 0x00000008U<01>OB_WRP_SECTOR_4 0x00000010U<01>OB_WRP_SECTOR_5 0x00000020U<01>OB_WRP_SECTOR_6 0x00000040U<01>OB_WRP_SECTOR_7 0x00000080U<01>OB_WRP_SECTOR_All 0x00000FFFU<01>OB_PCROP_SECTOR_0 0x00000001U<01>OB_PCROP_SECTOR_1 0x00000002U<01>OB_PCROP_SECTOR_2 0x00000004U<01>OB_PCROP_SECTOR_3 0x00000008U<01>OB_PCROP_SECTOR_4 0x00000010U<01>OB_PCROP_SECTOR_5 0x00000020U<01>OB_PCROP_SECTOR_6 0x00000040U<01>OB_PCROP_SECTOR_7 0x00000080U<01>OB_PCROP_SECTOR_All 0x00000FFFU<01>OB_PCROP_DESELECTED ((uint8_t)0x00)<01>OB_PCROP_SELECTED ((uint8_t)0x80)<01>FLASH_SECTOR_TOTAL 8U<01>IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))<01>IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || ((RANGE) == FLASH_VOLTAGE_RANGE_2) || ((RANGE) == FLASH_VOLTAGE_RANGE_3) || ((RANGE) == FLASH_VOLTAGE_RANGE_4))<01>IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))<01>IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))<01>IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1) || ((LEVEL) == OB_RDP_LEVEL_2))<01>IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))<01>IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))<01>IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>TypeEraseg#Banksg#Sectorg#NbSectorsg# VoltageRangeg#PFLASH_EraseInitTypeDef<12>>*<2A>OptionTypeg#WRPStateg#WRPSectorg#Banksg# RDPLevelg#BORLevelg#USERConfigH#PFLASH_OBProgramInitTypeDefqY*<2A> OptionTypeg#PCROPStateg#SectorsW#PFLASH_AdvOBProgramInitTypeDef<01><00><00><00>__STM32F4xx_FLASH_RAMFUNC_H |p ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.hstm32f4xx_hal_def.h<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<00><00><00>__STM32F4xx_HAL_FLASH_H XHAL_FLASH_ERROR_NONE 0x00000000UYHAL_FLASH_ERROR_RD 0x00000001UZHAL_FLASH_ERROR_PGS 0x00000002U[HAL_FLASH_ERROR_PGP 0x00000004U\HAL_FLASH_ERROR_PGA 0x00000008U]HAL_FLASH_ERROR_WRP 0x00000010U^HAL_FLASH_ERROR_OPERATION 0x00000020UfFLASH_TYPEPROGRAM_BYTE 0x00000000UgFLASH_TYPEPROGRAM_HALFWORD 0x00000001UhFLASH_TYPEPROGRAM_WORD 0x00000002UiFLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003UrFLASH_FLAG_EOP FLASH_SR_EOPsFLASH_FLAG_OPERR FLASH_SR_SOPtFLASH_FLAG_WRPERR FLASH_SR_WRPERRuFLASH_FLAG_PGAERR FLASH_SR_PGAERRvFLASH_FLAG_PGPERR FLASH_SR_PGPERRwFLASH_FLAG_PGSERR FLASH_SR_PGSERRyFLASH_FLAG_RDERR FLASH_SR_RDERR{FLASH_FLAG_BSY FLASH_SR_BSY<01>FLASH_IT_EOP FLASH_CR_EOPIE<01>FLASH_IT_ERR 0x02000000U<01>FLASH_PSIZE_BYTE 0x00000000U<01>FLASH_PSIZE_HALF_WORD 0x00000100U<01>FLASH_PSIZE_WORD 0x00000200U<01>FLASH_PSIZE_DOUBLE_WORD 0x00000300U<01>CR_PSIZE_MASK 0xFFFFFCFFU<01>RDP_KEY ((uint16_t)0x00A5)<01>FLASH_KEY1 0x45670123U<01>FLASH_KEY2 0xCDEF89ABU<01>FLASH_OPT_KEY1 0x08192A3BU<01>FLASH_OPT_KEY2 0x4C5D6E7FU<01>__HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))<01>__HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))<01>__HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)<01>__HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))<01>__HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)<01>__HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))<01>__HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)<01>__HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))<01>__HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; FLASH->ACR &= ~FLASH_ACR_ICRST; }while(0U)<01>__HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; FLASH->ACR &= ~FLASH_ACR_DCRST; }while(0U)<01>__HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))<01>__HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))<01>__HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))<01>__HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))<03><03><01>ACR_BYTE0_ADDRESS 0x40023C00U<01>OPTCR_BYTE0_ADDRESS 0x40023C14U<01>OPTCR_BYTE1_ADDRESS 0x40023C15U<01>OPTCR_BYTE2_ADDRESS 0x40023C16U<01>OPTCR_BYTE3_ADDRESS 0x40023C17U<01>IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_BYTE) || ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))<00><00> ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.hstm32f4xx_hal_def.hstm32f4xx_hal_flash_ex.hstm32f4xx_hal_flash_ramfunc.h,
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<13>FLASH_PROC_NONE FLASH_PROC_SECTERASE FLASH_PROC_MASSERASE FLASH_PROC_PROGRAM PFLASH_ProcedureTypeDef<12>3*<2A> ProcedureOnGoing#NbSectorsToErase#VoltageForErase
#Sector# Bank#Address#Locka#ErrorCode#tNtgtHPFLASH_ProcessTypeDeflJ<00><00><00>__STM32F4xx_HAL_PWR_EX_H HPWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOSJPWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1LPWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0<01>__HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { __IO uint32_t tmpreg = 0x00U; MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); UNUSED(tmpreg); } while(0U)<01>FPDS_BIT_NUMBER PWR_CR_FPDS_Pos<01>CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))<01>ODEN_BIT_NUMBER PWR_CR_ODEN_Pos<01>CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))<01>ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos<01>CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))<01>MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos<01>CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))<01>LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos<01>CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))<01>BRE_BIT_NUMBER PWR_CSR_BRE_Pos<01>CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))<01>IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))<01>IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)ti ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.hstm32f4xx_hal_def.h<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<00><00><00>__STM32F4xx_HAL_PWR_H CPWR_WAKEUP_PIN1 0x00000100UKPWR_PVDLEVEL_0 PWR_CR_PLS_LEV0LPWR_PVDLEVEL_1 PWR_CR_PLS_LEV1MPWR_PVDLEVEL_2 PWR_CR_PLS_LEV2NPWR_PVDLEVEL_3 PWR_CR_PLS_LEV3OPWR_PVDLEVEL_4 PWR_CR_PLS_LEV4PPWR_PVDLEVEL_5 PWR_CR_PLS_LEV5QPWR_PVDLEVEL_6 PWR_CR_PLS_LEV6RPWR_PVDLEVEL_7 PWR_CR_PLS_LEV7[PWR_PVD_MODE_NORMAL 0x00000000U\PWR_PVD_MODE_IT_RISING 0x00010001U]PWR_PVD_MODE_IT_FALLING 0x00010002U^PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U_PWR_PVD_MODE_EVENT_RISING 0x00020001U`PWR_PVD_MODE_EVENT_FALLING 0x00020002UaPWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003UjPWR_MAINREGULATOR_ON 0x00000000UkPWR_LOWPOWERREGULATOR_ON PWR_CR_LPDSsPWR_SLEEPENTRY_WFI ((uint8_t)0x01)tPWR_SLEEPENTRY_WFE ((uint8_t)0x02)uPWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03)~PWR_STOPENTRY_WFI ((uint8_t)0x01)PWR_STOPENTRY_WFE ((uint8_t)0x02)<01>PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03)<01>PWR_FLAG_WU PWR_CSR_WUF<01>PWR_FLAG_SB PWR_CSR_SBF<01>PWR_FLAG_PVDO PWR_CSR_PVDO<01>PWR_FLAG_BRR PWR_CSR_BRR<01>PWR_FLAG_VOSRDY PWR_CSR_VOSRDY<01>__HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))<01>__HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)<01>__HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); }while(0U)<01>__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); }while(0U)<01>__HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))<03><01>PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)<01>PWR_OFFSET (PWR_BASE - PERIPH_BASE)<01>PWR_CR_OFFSET 0x00U<01>PWR_CSR_OFFSET 0x04U<01>PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)<01>PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)<01>DBP_BIT_NUMBER PWR_CR_DBP_Pos<01>CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))<01>PVDE_BIT_NUMBER PWR_CR_PVDE_Pos<01>CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))<01>VOS_BIT_NUMBER PWR_CR_VOS_Pos<01>CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))<01>EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos<01>CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))<01>IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))<01>IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))<01>IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))<01>IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTR
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>PVDLevelg#Modeg#PPWR_PVDTypeDef<12>5<00><00><00>STM32F4xx_HAL_SPI_H <01>HAL_SPI_ERROR_NONE (0x00000000U)<01>HAL_SPI_ERROR_MODF (0x00000001U)<01>HAL_SPI_ERROR_CRC (0x00000002U)<01>HAL_SPI_ERROR_OVR (0x00000004U)<01>HAL_SPI_ERROR_FRE (0x00000008U)<01>HAL_SPI_ERROR_DMA (0x00000010U)<01>HAL_SPI_ERROR_FLAG (0x00000020U)<01>HAL_SPI_ERROR_ABORT (0x00000040U)<01>SPI_MODE_SLAVE (0x00000000U)<01>SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)<01>SPI_DIRECTION_2LINES (0x00000000U)<01>SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY<01>SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE<01>SPI_DATASIZE_8BIT (0x00000000U)<01>SPI_DATASIZE_16BIT SPI_CR1_DFF<01>SPI_POLARITY_LOW (0x00000000U)<01>SPI_POLARITY_HIGH SPI_CR1_CPOL<01>SPI_PHASE_1EDGE (0x00000000U)<01>SPI_PHASE_2EDGE SPI_CR1_CPHA<01>SPI_NSS_SOFT SPI_CR1_SSM<01>SPI_NSS_HARD_INPUT (0x00000000U)<01>SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)<01>SPI_BAUDRATEPRESCALER_2 (0x00000000U)<01>SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)<01>SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)<01>SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)<01>SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)<01>SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)<01>SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)<01>SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)<01>SPI_FIRSTBIT_MSB (0x00000000U)<01>SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST<01>SPI_TIMODE_DISABLE (0x00000000U)<01>SPI_TIMODE_ENABLE SPI_CR2_FRF<01>SPI_CRCCALCULATION_DISABLE (0x00000000U)<01>SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN<01>SPI_IT_TXE SPI_CR2_TXEIE<01>SPI_IT_RXNE SPI_CR2_RXNEIE<01>SPI_IT_ERR SPI_CR2_ERRIE<01>SPI_FLAG_RXNE SPI_SR_RXNE<01>SPI_FLAG_TXE SPI_SR_TXE<01>SPI_FLAG_BSY SPI_SR_BSY<01>SPI_FLAG_CRCERR SPI_SR_CRCERR<01>SPI_FLAG_MODF SPI_SR_MODF<01>SPI_FLAG_OVR SPI_SR_OVR<01>SPI_FLAG_FRE SPI_SR_FRE<01>SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)<01>__HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)<01>__HAL_SPI_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))<01>__HAL_SPI_DISABLE_IT(__HANDLE__,__INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))<01>__HAL_SPI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)<01>__HAL_SPI_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))<01>__HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))<01>__HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_modf = 0x00U; tmpreg_modf = (__HANDLE__)->Instance->SR; CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); UNUSED(tmpreg_modf); } while(0U)<01>__HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_ovr = 0x00U; tmpreg_ovr = (__HANDLE__)->Instance->DR; tmpreg_ovr = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_ovr); } while(0U)<01>__HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_fre = 0x00U; tmpreg_fre = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_fre); }while(0U)<01>__HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)<01>__HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)<01>SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)<01>SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)<01>SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)<01>SPI_CHECK_FLAG(__SR__,__FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)<01>SPI_CHECK_IT_SOURCE(__CR2__,__INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)<01>IS_SPI_M
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>,Modeg#Directiong#DataSizeg#CLKPolarityg# CLKPhaseg#NSSg#BaudRatePrescalerg#FirstBitg#TIModeg# CRCCalculationg#$CRCPolynomialg#(PSPI_InitTypeDef<12>T<13>HAL_SPI_STATE_RESET HAL_SPI_STATE_READY HAL_SPI_STATE_BUSY HAL_SPI_STATE_BUSY_TX HAL_SPI_STATE_BUSY_RX HAL_SPI_STATE_BUSY_TX_RX HAL_SPI_STATE_ERROR HAL_SPI_STATE_ABORT PHAL_SPI_StateTypeDef<12>c)<29>__SPI_HandleTypeDefXInstance<12>#Init<12>#pTxBuffPtr<12>#0TxXferSizeW#4TxXferCount<12>#6pRxBuffPtr<12>#8RxXferSizeW#<RxXferCount<12>#>O<>%<12>"dRxISRl#@O<>%<12>"}TxISR<12>#Dhdmatx<12>#Hhdmarx<12>#LLocka#PState#QErrorCode #T"<10>H"<12>tW"H"<12>"{t<12>tgPSPI_HandleTypeDef<12><01><00><00><00>STM32F4xx_HAL_TIM_EX_H NTIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0OTIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1PTIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0)STIM_TIM5_GPIO 0x00000000UTTIM_TIM5_LSI TIM_OR_TI4_RMP_0UTIM_TIM5_LSE TIM_OR_TI4_RMP_1VTIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)XTIM_TIM11_GPIO 0x00000000UYTIM_TIM11_HSE TIM_OR_TI1_RMP_1<01>IS_TIM_REMAP(INSTANCE,TIM_REMAP) ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || ((TIM_REMAP) == TIM_TIM5_LSI) || ((TIM_REMAP) == TIM_TIM5_LSE) || ((TIM_REMAP) == TIM_TIM5_RTC))) || (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_HSE))))ti ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.hstm32f4xx_hal_def.hp
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>IC1Polarityg#IC1Prescalerg#IC1Filterg#Commutation_Delayg# PTIM_HallSensor_InitTypeDef<12><<00><00><00>STM32F4xx_HAL_TIM_H <01>TIM_CLEARINPUTSOURCE_NONE 0x00000000U<01>TIM_CLEARINPUTSOURCE_ETR 0x00000001U<01>TIM_DMABASE_CR1 0x00000000U<01>TIM_DMABASE_CR2 0x00000001U<01>TIM_DMABASE_SMCR 0x00000002U<01>TIM_DMABASE_DIER 0x00000003U<01>TIM_DMABASE_SR 0x00000004U<01>TIM_DMABASE_EGR 0x00000005U<01>TIM_DMABASE_CCMR1 0x00000006U<01>TIM_DMABASE_CCMR2 0x00000007U<01>TIM_DMABASE_CCER 0x00000008U<01>TIM_DMABASE_CNT 0x00000009U<01>TIM_DMABASE_PSC 0x0000000AU<01>TIM_DMABASE_ARR 0x0000000BU<01>TIM_DMABASE_RCR 0x0000000CU<01>TIM_DMABASE_CCR1 0x0000000DU<01>TIM_DMABASE_CCR2 0x0000000EU<01>TIM_DMABASE_CCR3 0x0000000FU<01>TIM_DMABASE_CCR4 0x00000010U<01>TIM_DMABASE_BDTR 0x00000011U<01>TIM_DMABASE_DCR 0x00000012U<01>TIM_DMABASE_DMAR 0x00000013U<01>TIM_EVENTSOURCE_UPDATE TIM_EGR_UG<01>TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G<01>TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G<01>TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G<01>TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G<01>TIM_EVENTSOURCE_COM TIM_EGR_COMG<01>TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG<01>TIM_EVENTSOURCE_BREAK TIM_EGR_BG<01>TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U<01>TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P<01>TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)<01>TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP<01>TIM_ETRPOLARITY_NONINVERTED 0x00000000U<01>TIM_ETRPRESCALER_DIV1 0x00000000U<01>TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0<01>TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1<01>TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS<01>TIM_COUNTERMODE_UP 0x00000000U<01>TIM_COUNTERMODE_DOWN TIM_CR1_DIR<01>TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0<01>TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1<01>TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS<01>TIM_CLOCKDIVISION_DIV1 0x00000000U<01>TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0<01>TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1<01>TIM_OUTPUTSTATE_DISABLE 0x00000000U<01>TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E<01>TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U<01>TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE<01>TIM_OCFAST_DISABLE 0x00000000U<01>TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE<01>TIM_OUTPUTNSTATE_DISABLE 0x00000000U<01>TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE<01>TIM_OCPOLARITY_HIGH 0x00000000U<01>TIM_OCPOLARITY_LOW TIM_CCER_CC1P<01>TIM_OCNPOLARITY_HIGH 0x00000000U<01>TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP<01>TIM_OCIDLESTATE_SET TIM_CR2_OIS1<01>TIM_OCIDLESTATE_RESET 0x00000000U<01>TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N<01>TIM_OCNIDLESTATE_RESET 0x00000000U<01>TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING<01>TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING<01>TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE<01>TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING<01>TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING<01>TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0<01>TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1<01>TIM_ICSELECTION_TRC TIM_CCMR1_CC1S<01>TIM_ICPSC_DIV1 0x00000000U<01>TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0<01>TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1<01>TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC<01>TIM_OPMODE_SINGLE TIM_CR1_OPM<01>TIM_OPMODE_REPETITIVE 0x00000000U<01>TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0<01>TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1<01>TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)<01>TIM_IT_UPDATE TIM_DIER_UIE<01>TIM_IT_CC1 TIM_DIER_CC1IE<01>TIM_IT_CC2 TIM_DIER_CC2IE<01>TIM_IT_CC3 TIM_DIER_CC3IE<01>TIM_IT_CC4 TIM_DIER_CC4IE<01>TIM_IT_COM TIM_DIER_COMIE<01>TIM_IT_TRIGGER TIM_DIER_TIE<01>TIM_IT_BREAK TIM_DIER_BIE<01>TIM_COMMUTATION_TRGI TIM_CR2_CCUS<01>TIM_COMMUTATION_SOFTWARE 0x00000000U<01>TIM_DMA_UPDATE TIM_DIER_UDE<01>TIM_DMA_CC1 TIM_DIER_CC1DE<01>TIM_DMA_CC2 TIM_DIER_CC2DE<01>TIM_DMA_CC3 TIM_DIER_CC3DE<01>TIM_DMA_CC4 TIM_DIER_CC4DE<01>TIM_DMA_COM TIM_DIER_COMDE<01>TIM_DMA_TRIGGER TIM_DIER_TDE<01>TIM_CCDMAREQUE
__HAL_TIM_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))<01>
__HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)<01>
__HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0)<01>
__HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)<01>
__HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0)<01>
__HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)<01>
__HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0)<01>
__HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)<01>
__HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))<01> __HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))<01> __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))<01> __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))<01> __HAL_TIM_ENABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))<01> __HAL_TIM_DISABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))<01> __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)<01> __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)<01> __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0)<01> __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__,__CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))<01> TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))<01> TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))<01> IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))<01> IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR))<01> IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))<01> IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))<01> IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION

../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>Prescalerg#CounterModeg#Periodg#ClockDivisiong# RepetitionCounterg#AutoReloadPreloadg#PTIM_Base_InitTypeDef<12>J*<2A>OCModeg#Pulseg#OCPolarityg#OCNPolarityg# OCFastModeg#OCIdleStateg#OCNIdleStateg#PTIM_OC_InitTypeDef<12>j*<2A>$OCModeg#Pulseg#OCPolarityg#OCNPolarityg# OCIdleStateg#OCNIdleStateg#ICPolarityg#ICSelectiong#ICFilterg# PTIM_OnePulse_InitTypeDef:<01>*<2A>ICPolarityg#ICSelectiong#ICPrescalerg#ICFilterg# PTIM_IC_InitTypeDef<01>*<2A>$EncoderModeg#IC1Polarityg#IC1Selectiong#IC1Prescalerg# IC1Filterg#IC2Polarityg#IC2Selectiong#IC2Prescalerg#IC2Filterg# PTIM_Encoder_InitTypeDef~<01>*<2A> ClockSourceg#ClockPolarityg#ClockPrescalerg#ClockFilterg# PTIM_ClockConfigTypeDef`<01>*<2A>
ClearInputStateg#ClearInputSourceg#ClearInputPolarityg#ClearInputPrescalerg# ClearInputFilterg#PTIM_ClearInputConfigTypeDef<12><01>*<2A> MasterOutputTriggerg#MasterSlaveModeg#PTIM_MasterConfigTypeDef<12><01>*<2A> SlaveModeg#InputTriggerg#TriggerPolarityg#TriggerPrescalerg# TriggerFilterg#PTIM_SlaveConfigTypeDef<12><01>*<2A> OffStateRunModeg#OffStateIDLEModeg#LockLevelg#DeadTimeg# BreakStateg#BreakPolarityg#BreakFilterg#AutomaticOutputg#PTIM_BreakDeadTimeConfigTypeDef~<01><13>HAL_TIM_STATE_RESET HAL_TIM_STATE_READY HAL_TIM_STATE_BUSY HAL_TIM_STATE_TIMEOUT HAL_TIM_STATE_ERROR PHAL_TIM_StateTypeDef[<01><13>HAL_TIM_CHANNEL_STATE_RESET HAL_TIM_CHANNEL_STATE_READY HAL_TIM_CHANNEL_STATE_BUSY PHAL_TIM_ChannelStateTypeDef<12><01><13>HAL_DMA_BURST_STATE_RESET HAL_DMA_BURST_STATE_READY HAL_DMA_BURST_STATE_BUSY PHAL_TIM_DMABurstStateTypeDefv<01><13>HAL_TIM_ACTIVE_CHANNEL_1 HAL_TIM_ACTIVE_CHANNEL_2 HAL_TIM_ACTIVE_CHANNEL_3 HAL_TIM_ACTIVE_CHANNEL_4 HAL_TIM_ACTIVE_CHANNEL_CLEARED PHAL_TIM_ActiveChannel<12><01>*<2A>HInstance[
#Initx#Channel<12> #<03>a
hdma<12> # Locka#<Stateg
#=<03>k
ChannelState
#><03>k
ChannelNState'
#BDMABurstStateo
#F"<10>"{t<12>tRt<12>PTIM_HandleTypeDef<12> <01><00><00><00>__STM32F4xx_HAL_UART_H <01>HAL_UART_ERROR_NONE 0x00000000U<01>HAL_UART_ERROR_PE 0x00000001U<01>HAL_UART_ERROR_NE 0x00000002U<01>HAL_UART_ERROR_FE 0x00000004U<01>HAL_UART_ERROR_ORE 0x00000008U<01>HAL_UART_ERROR_DMA 0x00000010U<01>UART_WORDLENGTH_8B 0x00000000U<01>UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)<01>UART_STOPBITS_1 0x00000000U<01>UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)<01>UART_PARITY_NONE 0x00000000U<01>UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)<01>UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))<01>UART_HWCONTROL_NONE 0x00000000U<01>UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)<01>UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)<01>UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))<01>UART_MODE_RX ((uint32_t)USART_CR1_RE)<01>UART_MODE_TX ((uint32_t)USART_CR1_TE)<01>UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))<01>UART_STATE_DISABLE 0x00000000U<01>UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)<01>UART_OVERSAMPLING_16 0x00000000U<01>UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)<01>UART_LINBREAKDETECTLENGTH_10B 0x00000000U<01>UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)<01>UART_WAKEUPMETHOD_IDLELINE 0x00000000U<01>UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)<01>UART_FLAG_CTS ((uint32_t)USART_SR_CTS)<01>UART_FLAG_LBD ((uint32_t)USART_SR_LBD)<01>UART_FLAG_TXE ((uint32_t)USART_SR_TXE)<01>UART_FLAG_TC ((uint32_t)USART_SR_TC)<01>UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)<01>UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)<01>UART_FLAG_ORE ((uint32_t)USART_SR_ORE)<01>UART_FLAG_NE ((uint32_t)USART_SR_NE)<01>UART_FLAG_FE ((uint32_t)USART_SR_FE)<01>UART_FLAG_PE ((uint32_t)USART_SR_PE)<01>UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))<01>UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))<01>UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))<01>UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))<01>UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))<01>UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))<01>UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))<01>UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))<01>HAL_UART_RECEPTION_STANDARD (0x00000000U)<01>HAL_UART_RECEPTION_TOIDLE (0x00000001U)<01>HAL_UART_RXEVENT_TC (0x00000000U)<01>HAL_UART_RXEVENT_HT (0x00000001U)<01>HAL_UART_RXEVENT_IDLE (0x00000002U)<01>__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U)<01>__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)<01>__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))<01>__HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))<01>__HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{ __IO uint32_t tmpreg = 0x00U; tmpreg = (__HANDLE__)->Instance->SR; tmpreg = (__HANDLE__)->Instance->DR; UNUSED(tmpreg); } while(0U)<01>__HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))<01>__HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 &= ~
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM*<2A>BaudRateg#WordLengthg#StopBitsg#Parityg# Modeg#HwFlowCtlg#OverSamplingg#PUART_InitTypeDef<12>K<13>HAL_UART_STATE_RESET HAL_UART_STATE_READY HAL_UART_STATE_BUSY $HAL_UART_STATE_BUSY_TX !HAL_UART_STATE_BUSY_RX "HAL_UART_STATE_BUSY_TX_RX #HAL_UART_STATE_TIMEOUT <0B>HAL_UART_STATE_ERROR <0B>PHAL_UART_StateTypeDef<12><01>PHAL_UART_RxTypeTypeDefg<01>PHAL_UART_RxEventTypeTypeDefg<01>)<29>__UART_HandleTypeDefHInstance<12>#Inits#pTxBuffPtr<12># TxXferSizeW#$TxXferCount<12>#&pRxBuffPtr<12>#(RxXferSizeW#,RxXferCount<12>#.ReceptionType#0RxEventType#4hdmatx #8hdmarx #<Locka#@gState#ARxState#BErrorCode#D"LH"<12>tW"Htxt<12>"{tZtgPUART_HandleTypeDef<12><01><00><00><00>__STM32F4xx_HAL_CONF_H &HAL_MODULE_ENABLED )HAL_ADC_MODULE_ENABLED AHAL_SPI_MODULE_ENABLED BHAL_TIM_MODULE_ENABLED CHAL_UART_MODULE_ENABLED THAL_GPIO_MODULE_ENABLED UHAL_EXTI_MODULE_ENABLED VHAL_DMA_MODULE_ENABLED WHAL_RCC_MODULE_ENABLED XHAL_FLASH_MODULE_ENABLED YHAL_PWR_MODULE_ENABLED ZHAL_CORTEX_MODULE_ENABLED cHSE_VALUE 25000000UgHSE_STARTUP_TIMEOUT 100UpHSI_VALUE ((uint32_t)16000000U)wLSI_VALUE 32000ULSE_VALUE 32768U<01>LSE_STARTUP_TIMEOUT 5000U<01>EXTERNAL_CLOCK_VALUE 12288000U<01>VDD_VALUE 3300U<01>TICK_INT_PRIORITY 15U<01>USE_RTOS 0U<01>PREFETCH_ENABLE 1U<01>INSTRUCTION_CACHE_ENABLE 1U<01>DATA_CACHE_ENABLE 1U<01>USE_HAL_ADC_REGISTER_CALLBACKS 0U<01>USE_HAL_CAN_REGISTER_CALLBACKS 0U<01>USE_HAL_CEC_REGISTER_CALLBACKS 0U<01>USE_HAL_CRYP_REGISTER_CALLBACKS 0U<01>USE_HAL_DAC_REGISTER_CALLBACKS 0U<01>USE_HAL_DCMI_REGISTER_CALLBACKS 0U<01>USE_HAL_DFSDM_REGISTER_CALLBACKS 0U<01>USE_HAL_DMA2D_REGISTER_CALLBACKS 0U<01>USE_HAL_DSI_REGISTER_CALLBACKS 0U<01>USE_HAL_ETH_REGISTER_CALLBACKS 0U<01>USE_HAL_HASH_REGISTER_CALLBACKS 0U<01>USE_HAL_HCD_REGISTER_CALLBACKS 0U<01>USE_HAL_I2C_REGISTER_CALLBACKS 0U<01>USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U<01>USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U<01>USE_HAL_I2S_REGISTER_CALLBACKS 0U<01>USE_HAL_IRDA_REGISTER_CALLBACKS 0U<01>USE_HAL_LPTIM_REGISTER_CALLBACKS 0U<01>USE_HAL_LTDC_REGISTER_CALLBACKS 0U<01>USE_HAL_MMC_REGISTER_CALLBACKS 0U<01>USE_HAL_NAND_REGISTER_CALLBACKS 0U<01>USE_HAL_NOR_REGISTER_CALLBACKS 0U<01>USE_HAL_PCCARD_REGISTER_CALLBACKS 0U<01>USE_HAL_PCD_REGISTER_CALLBACKS 0U<01>USE_HAL_QSPI_REGISTER_CALLBACKS 0U<01>USE_HAL_RNG_REGISTER_CALLBACKS 0U<01>USE_HAL_RTC_REGISTER_CALLBACKS 0U<01>USE_HAL_SAI_REGISTER_CALLBACKS 0U<01>USE_HAL_SD_REGISTER_CALLBACKS 0U<01>USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U<01>USE_HAL_SDRAM_REGISTER_CALLBACKS 0U<01>USE_HAL_SRAM_REGISTER_CALLBACKS 0U<01>USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U<01>USE_HAL_SMBUS_REGISTER_CALLBACKS 0U<01>USE_HAL_SPI_REGISTER_CALLBACKS 0U<01>USE_HAL_TIM_REGISTER_CALLBACKS 0U<01>USE_HAL_UART_REGISTER_CALLBACKS 0U<01>USE_HAL_USART_REGISTER_CALLBACKS 0U<01>USE_HAL_WWDG_REGISTER_CALLBACKS 0U<01>MAC_ADDR0 2U<01>MAC_ADDR1 0U<01>MAC_ADDR2 0U<01>MAC_ADDR3 0U<01>MAC_ADDR4 0U<01>MAC_ADDR5 0U<01>ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE<01>ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE<01>ETH_RXBUFNB 4U<01>ETH_TXBUFNB 4U<01>DP83848_PHY_ADDRESS <01>PHY_RESET_DELAY 0x000000FFU<01>PHY_CONFIG_DELAY 0x00000FFFU<01>PHY_READ_TO 0x0000FFFFU<01>PHY_WRITE_TO 0x0000FFFFU<01>PHY_BCR ((uint16_t)0x0000U)<01>PHY_BSR ((uint16_t)0x0001U)<01>PHY_RESET ((uint16_t)0x8000U)<01>PHY_LOOPBACK ((uint16_t)0x4000U)<01>PHY_FULLDUPLEX_100M ((uint16_t)0x2100U)<01>PHY_HALFDUPLEX_100M ((uint16_t)0x2000U)<01>PHY_FULLDUPLEX_10M ((uint16_t)0x0100U)<01>PHY_HALFDUPLEX_10M ((uint16_t)0x0000U)<01>PHY_AUTONEGOTIATION ((uint16_t)0x1000U)<01>PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U)<01>PHY_POWERDOWN ((uint16_t)0x0800U)<01>PHY_ISOLATE ((uint16_t)0x0400U)<01>PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020
<03> <03> <01>assert_param(expr) ((void)0U)lb ../Core/Inc/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf.hstm32f4xx_hal_rcc.hstm32f4xx_hal_gpio.hstm32f4xx_hal_exti.hstm32f4xx_hal_dma.hstm32f4xx_hal_cortex.hstm32f4xx_hal_adc.hstm32f4xx_hal_flash.hstm32f4xx_hal_pwr.hstm32f4xx_hal_spi.hstm32f4xx_hal_tim.hstm32f4xx_hal_uart.h<01>
../Core/Inc/stm32f4xx_hal_conf.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<00><00><00>__MAIN_H lb ../Core/Inc/../Drivers/STM32F4xx_HAL_Driver/Inc/main.hstm32f4xx_hal.h<01>
../Core/Inc/main.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARM<00><00><00>XM ../Core/Inc/../Core/Src/stm32f4xx_hal_msp.cmain.h<01>
../Core/Src/stm32f4xx_hal_msp.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] E:\projects\programs\STM32_Programs\F411_programs\F411CEU6\Power_Pico\Power_Pico\MDK-ARMtg"<10>""s
"<00>!/!I$ > %%%% %C
%C % % %%%C%C&I  ((      1 1 1 1 I8  I I8 4 ! I8 "I#7I$I%I&I 'I(I) * +,-./4  04 14 24 34 44 5.:;9? I6.:;9? 7.:;9G8.:;9? I 9.:;9? :.:;9G ;.:;9? I<.:;9? =.:;9G>.:;9? I@?.:;9? @@.:;9G@A.:;9? I@
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K.1L.< 4 I? M.< 4 ? NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M4.fp.sp --fpu=VFPv4_SP_D16 --output=power_pico\stm32f4xx_hal_msp.o --vfemode=force
Input Comments:p3b9c-3Component: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M4.fp.sp --fpu=VFPv4_SP_D16 --apcs=/interwork/interwork --divide stm32f4xx_hal_msp.oComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]ArmCC --c99 --split_sections --debug -c -opower_pico\stm32f4xx_hal_msp.o --depend=power_pico\stm32f4xx_hal_msp.d --cpu=Cortex-M4.fp.sp --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I.\RTE\_power_pico -I"E:\Program Files\Keil_v5\ARM\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include" -I"E:\Program Files\Keil_v5\ARM\Packs\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include" -D__UVISION_VERSION=538 -D_RTE_ -DSTM32F411xE -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F411xE --omf_browse=power_pico\stm32f4xx_hal_msp.crf ../Core/Src/stm32f4xx_hal_msp.c<00>/<00>/<00>/<00>/<00>/<00>/<00>/T<00>/<00>/4<00>/<00>/<00>/<00>/^<00>/ <00>/n <00>/
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